Datasheet

Confidential for truly Only
11.03.2009 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies
6-15
0x4801 MIPI CTRL 01 0x0F RW
MIPI Control 01
Bit[7]: Long packet data type manual enable
0: Use mipi_dt
1: Use dt_man_o as long packet data
(see register 0x4814[5:0])
Bit[6]: Short packet data type manual enable
1: Use dt_spkt as short packet data
(see register 0x4815[5:0])
Bit[5]: Short packet WORD COUNTER manual
enable
0: Use frame counter or line counter
1: Select spkt_wc_reg_o
(see {0x4812, 0x4813})
Bit[4]: PH bit order for ECC
0: {DI[7:0],WC[7:0],WC[15:8]}
1: {DI[0:7],WC[0:7],WC[8:15]}
Bit[3]: PH byte order for ECC
0: {DI,WC_l,WC_h}
1: {DI,WC_h,WC_l}
Bit[2]: PH byte order2 for ECC
0: {DI,WC}
1: {WC,DI}
Bit[1]: mark1_en1
1: After each rst release, lane 1 should
send mark1 for wkup_dly_o when
mipi_sys_susp =1
Bit[0]: mark1_en2
1: After each reset release, lane 2
should send mark1 for wkup_dly_o
when mipi_sys_susp=1
table 6-9 MIPI transmitter registers (sheet 2 of 8)
address register name
default
value R/W description