Datasheet

Confidential for truly Only
color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology
OV5647
proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.0
6.8 mobile industry processor interface (MIPI)
MIPI provides a single uni-directional clock lane and two bi-directional data lane solution for communication links
between components inside a mobile device. The two data lanes have full support for HS (uni-directional) and LP
(bi-directional) data transfer mode.
table 6-9 MIPI transmitter registers (sheet 1 of 8)
address register name
default
value R/W description
0x4800 MIPI CTRL 00 0x04 RW
MIPI Control 00
Bit[7]: mipi_hs_only
0: MIPI can support CD and ESCAPE
mode
1: MIPI always in High Speed mode
Bit[6]: ck_mark1_en
1: Enable clock lane mark1 when
resume
Bit[5]: Clock lane gate enable
0: Clock lane is free running
1: Gate clock lane when no packet to
transmit
Bit[4]: Line sync enable
0: Do not send line short packet for
each line
1: Send line short packet for each line
Bit[3]: Lane select
0: Use lane1 as default data lane
1: Use lane2 as default data lane
Bit[2]: Idle status
0: MIPI bus will be LP00 when no
packet to transmit
1: MIPI bus will be LP11 when no
packet to transmit
Bit[1]: Clock lane first bits
0: Output 0x55
1: Output 0xAA
Bit[0]: Clock lane disable
1: Manually set clock lane to low power
mode