Datasheet

Confidential for truly Only
11.03.2009 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies
6-11
0x4703 DVP_HSYVSY_NEG_WIDTH 0x00 RW
Bit[7:0]: VSYNC length in terms of pixel
count[7:0]
0x4704 DVP VSYNC MODE 0x00 RW
Bit[3:2]: r_vsyncount_sel
Bit[1]: r_vsync3_mod
Bit[0]: r_vsync2_mod
0x4705 DVP_EOF_VSYNC DELAY 0x00 RW
Bit[7:0]: eof_vsync_delay[23:16]
SOF/EOF negative edge to
VSYNC positive edge delay
0x4706 DVP_EOF_VSYNC DELAY 0x00 RW
Bit[7:0]: eof_vsync_delay[15:8]
SOF/EOF negative edge to
VSYNC positive edge dealy
0x4707 DVP_EOF_VSYNC DELAY 0x00 RW
Bit[7:0]: eof_vsync_delay[7:0]
SOF/EOF negative edge to
VSYNC positive edge delay
0x4708 DVP_POL_CTRL 0x01 RW
Bit[7]: Clock DDR mode enable
Bit[5]: VSYNC gated clock enable
Bit[4]: HREF gated clock enable
Bit[3]: No first for FIFO
Bit[2]: HREF polarity reverse
Bit[1]: VSYNC polarity reverse
Bit[0]: PCLK polarity reverse
0x4709 BIT_TEST_PATTERN 0x00 RW
Bit[7]: FIFO bypass mode
Bit[6:4]: Data bit swap
Bit[3]: Bit test mode
Bit[2]: 10-bit bit test
Bit[1]: 8-bit bit test
Bit[0]: Bit test enable
0x470A DVP_BYP_CTRL 0x00 RW Bit[7:0]: bypass_ctrl[15:8]
0x470B DVP_BYP_CTRL 0x00 RW Bit[7:0]: bypass_ctrl[7:0]
0x470C DVP_BYP_SEL 0x00 RW
Bit[4]: HREF select
Bit[3:0]: Bypass select
table 6-7 system control registers (sheet 2 of 2)
address register name
default
value R/W description