Datasheet

Confidential for truly Only
color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology
OV5647
proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.0
6.6 frame control (FC)
Frame control (FC) is used to mask some specified frame by setting the appropriate registers.
6.7 digital video port (DVP)
The Digital Video Port (DVP) provides 10-bit parallel data output in all formats supported and extended features including
compression mode, HSYNC mode, CCIR656 mode, and test pattern output.
table 6-6 frame control registers
address register name
default
value R/W description
0x4200 FRAME CONTROL00 0x00 RW
Bit[2]: fcnt_eof_sel
Bit[1]: fcnt_mask_dis
Bit[0]: Frame counter reset
0x4201 FRAME CONTROL01 0x00 RW
Control Passed Frame Number
Bit[3:0]: Frame ON number
When both ON and OFF numbers are set
to 0x00, frame control is in bypass mode
0x4202 FRAME CONTROL02 0x00 RW
Control Masked Frame Number
Bit[3:0]: Frame OFF number
When both ON and OFF numbers are set
to 0x00, frame control is in bypass mode
0x4203 FRAME CONTROL03 0x00 RW
Bit[6]: rblue_mask_dis
Bit[5]: data_mask_dis
Bit[4]: valid_mask_dis
Bit[3]: href_mask_dis
Bit[2]: eof_mask_dis
Bit[1]: sof_mask_dis
Bit[0]: all_mask_dis
table 6-7 system control registers (sheet 1 of 2)
address register name
default
value R/W description
0x4700 DVP MODE SELECT 0x04 RW
Bit[3]: CCIR v select
Bit[2]: CCIR f select
Bit[1]: CCIR656 mode enable
Bit[0]: HSYNC mode enable
0x4701
DVP VSYNC WIDTH
CONTRL
0x01 RW VSYNC Width (in terms of number of lines)
0x4702 DVP_HSYVSY_NEG_WIDTH 0x01 RW
Bit[7:0]: VSYNC length in terms of pixel
count[15:8]