Datasheet

Confidential for truly Only
11.03.2009 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies
6-5
6.2 SCCB
table 6-2 system control registers
address register name
default
value R/W description
0x3100 SCCB CTRL 0x00 RW
Bit[3]: r_sda_dly_en
Bit[2:0]: r_sda_dly
0x3101 SCCB OPT 0x12 RW
Bit[4]: en_ss_addr_inc
Bit[3]: r_sda_byp_sync
0: Two clock stage SYNC
for sda_i
1: No sync for sda_i
Bit[2]: r_scl_byp_sync
0: Two clock stage SYNC
for scl_i
1: No sync for scl_i
Bit[1]: r_msk_glitch
Bit[0]: r_msk_stop
0x3102 SCCB FILTER 0x00 RW
Bit[7:4]: r_sda_num
Bit[3:0]: r_scl_num
0x3103 SCCB SYSREG 0x00 RW
Bit[6]: ctrl_rst_mipisc
Bit[5]: ctrl_rst_srb
Bit[4]: ctrl_rst_sccb_s
Bit[3]: ctrl_rst_pon_sccb_s
Bit[2]: ctrl_rst_clkmod
Bit[1]: ctrl_rst_mipi_phy_rst_o
Bit[0]: ctrl_pll_rst_o
0x3104 PWUP DIS 0x01 RW
Bit[4]: r_srb_clk_syn_en
Bit[3]: pwup_dis2
Bit[2]: pwup_dis1
Bit[1]: pll_clk_sel
Bit[0]: pwup_dis0
0x3105 PADCLK DIV 0x11 RW
Bit[5]: SCLK use p_clk_i
Bit[4]: Sleep enable
Bit[3:0]: PADCLK divider for SCCB
0x3106 SRB CTRL 0xF9 RW
Bit[3:2]: PLL clock divider
00: pll_sclk
01: pll_sclk/2
10: pll_sclk/4
11: pll_sclk
Bit[1]: rst_arb
1: Reset arbiter
Bit[0]: sclk_arb
1: Enable SCLK to arbiter