Datasheet
Table Of Contents
- applications
- features
- key specifications
- table of contents
- list of figures
- list of tables
- 1 signal descriptions
- 2 system level description
- 3 block level description
- 4 image sensor core digital functions
- 4.1 mirror and flip
- 4.2 image windowing
- 4.3 test pattern
- 4.4 50/60Hz detection
- 4.5 AEC and AGC algorithms
- 4.6 AEC/AGC steps
- 4.7 black level calibration (BLC)
- 4.8 strobe flash and frame exposure
- 4.9 xenon flash control
- 4.10 frame exposure (FREX) mode
- 4.11 FREX strobe flash control
- 4.12 one-time programmable (OTP) memory
- 5 image sensor processor digital functions
- 6 image sensor output interface digital functions
- 7 register tables
- table 7-1 system control registers (sheet 1 of 5)
- table 7-2 SCCB registers (sheet 1 of 2)
- table 7-3 group hold control registers
- table 7-4 AEC/AGC 1 registers
- table 7-5 system timing registers (sheet 1 of 3)
- table 7-6 AEC/AGC 2 registers (sheet 1 of 3)
- table 7-7 STROBE/frame exposure control registers (sheet 1 of 2)
- table 7-8 50/60 HZ DETECTION registers
- table 7-9 OTP control registers (sheet 1 of 2)
- table 7-10 BLC registers (sheet 1 of 3)
- table 7-11 frame control registers
- table 7-12 DVP registers (sheet 1 of 2)
- table 7-13 MIPI top registers (sheet 1 of 11)
- table 7-14 ISPFC registers
- table 7-15 ISP TOP control registers (sheet 1 of 6)
- table 7-16 AWB registers (sheet 1 of 3)
- table 7-17 average registers (sheet 1 of 2)
- table 7-18 DPC registers
- table 7-19 LENC registers (sheet 1 of 4)
- table 7-20 cluster DPC registers (sheet 1 of 2)
- table 7-21 windows registers
- table 7-22 AEC/AGC 3 registers
- 8 operating specifications
- 9 mechanical specifications
- 10 optical specifications
- revision history
Confidential for truly Only
color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology
OV5647
proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.0
0x3034
SC_CMMN_PLL_
CTRL0
0x1A RW
Bit[6:4]: pll_charge_pump
Bit[3:0]: mipi_bit_mode
0000: 8 bit mode
0001: 10 bit mode
Others: Reserved to future use
0x3035
SC_CMMN_PLL_
CTRL1
0x11 RW
Bit[7:4]: system_clk_div
Will slow down all clocks
Bit[3:0]: scale_divider_mipi
MIPI PCLK/SERCLK can be
slowed down when image is
scaled down
0x3036
SC_CMMN_PLL_
MULTIPLIER
0x69 RW
Bit[7:0]: PLL_multiplier (4~252) can be
any integer during 4~127 and only
even integer during 128~252
0x3037
SC_CMMN_PLL_
CTR13
0x03 RW
Bit[4]: pll_root_div
0: Bypass
1: /2
Bit[3:0]: pll_prediv
1, 2, 3, 4, 6, 8
0x3039
SC_CMMN_PLL_
CTRL_R
0x00 RW Bit[7]: pll_bypass
0x303A
SC_CMMN_PLLS_
CTRL0
0x00 RW Bit[7]: plls_bypass
0x303B
SC_CMMN_PLLS_
CTRL1
0x19 RW Bit[4:0]: plls_multiplier
0x303C
SC_CMMN_PLLS_
CTRL2
0x11 RW
Bit[6:4]: plls_cp
Bit[3:0]: plls_sys_div
0x303D
SC_CMMN_PLLS_
CTRL3
0x30 RW
Bit[5:4]: plls_pre_div
00: /1
01: /1.5
10: /2
11: /3
Bit[2]: plls_div_r
0: /1
1: /2
Bit[1:0]: plls_seld5
00: /1
01: /1
10: /2
11: /2.5
table 6-1 system control registers (sheet 4 of 4)
address
register name
default
value
R/W
description