Datasheet
Table Of Contents
- applications
- features
- key specifications
- table of contents
- list of figures
- list of tables
- 1 signal descriptions
- 2 system level description
- 3 block level description
- 4 image sensor core digital functions
- 4.1 mirror and flip
- 4.2 image windowing
- 4.3 test pattern
- 4.4 50/60Hz detection
- 4.5 AEC and AGC algorithms
- 4.6 AEC/AGC steps
- 4.7 black level calibration (BLC)
- 4.8 strobe flash and frame exposure
- 4.9 xenon flash control
- 4.10 frame exposure (FREX) mode
- 4.11 FREX strobe flash control
- 4.12 one-time programmable (OTP) memory
- 5 image sensor processor digital functions
- 6 image sensor output interface digital functions
- 7 register tables
- table 7-1 system control registers (sheet 1 of 5)
- table 7-2 SCCB registers (sheet 1 of 2)
- table 7-3 group hold control registers
- table 7-4 AEC/AGC 1 registers
- table 7-5 system timing registers (sheet 1 of 3)
- table 7-6 AEC/AGC 2 registers (sheet 1 of 3)
- table 7-7 STROBE/frame exposure control registers (sheet 1 of 2)
- table 7-8 50/60 HZ DETECTION registers
- table 7-9 OTP control registers (sheet 1 of 2)
- table 7-10 BLC registers (sheet 1 of 3)
- table 7-11 frame control registers
- table 7-12 DVP registers (sheet 1 of 2)
- table 7-13 MIPI top registers (sheet 1 of 11)
- table 7-14 ISPFC registers
- table 7-15 ISP TOP control registers (sheet 1 of 6)
- table 7-16 AWB registers (sheet 1 of 3)
- table 7-17 average registers (sheet 1 of 2)
- table 7-18 DPC registers
- table 7-19 LENC registers (sheet 1 of 4)
- table 7-20 cluster DPC registers (sheet 1 of 2)
- table 7-21 windows registers
- table 7-22 AEC/AGC 3 registers
- 8 operating specifications
- 9 mechanical specifications
- 10 optical specifications
- revision history
Confidential for truly Only
11.03.2009 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies
6-3
0x3018
SC_CMMN_MIPI_
SC_CTRL
0x58 RW
Bit[7:5]: mipi_lane_mode
0: One lane mode
1: Two lane mode
Bit[4]: r_phy_pd_mipi
1: Power donw PHY HS TX
Bit[3]: r_phy_pd_lprx
1: Power down PHY LP RX
module
Bit[2]: mipi_en
0: DVP enable
1: MIPI enable
Bit[1]: mipi_susp_reg
MIPI system Suspend register
1: suspend
Bit[0]: lane_dis_op
0: Use mipi_release1/2 and
lane_disable1/2 to disable
two data lane
1: Use lane_disable1/2 to
disable two data lane
0x3019
SC_CMMN_MIPI_
SC_CTRL
0x10 RW
Bit[7:0]: MIPI ULPS resume mark1 detect
length
0x3021
SC_CMMN_MISC_
CTRL
0x23 RW
Bit[5]: fst_stby_ctr
1: Software standby enter at
l_blk
0: Software standby enter at
v_blk
Bit[4]: mipi_ctr_en
1: Enable MIPI remote reset
and suspend control SC
0: Disable the function
Bit[3]: mipi_rst_sel
0: MIPI remote reset all
registers
1: MIPI remote reset all digital
modules
Bit[2]: gpio_pclk_en
Bit[1]: frex_ef_sel
Bit[0]: cen_global_o
0x3022
SC_CMMN_MIPI_
SC_CTRL
0x00 RW
Bit[3]: lptx_ck_opt
Bit[2]: pull_down_clk_lane
Bit[1]: pull_down_data_lane2
Bit[0]: pull_down_data_lane1
0x302A SC_CMMN_SUB_ID – R
Bit[7:4]: Process
Bit[3:0]: Version
table 6-1 system control registers (sheet 3 of 4)
address
register name
default
value
R/W
description