Datasheet
Table Of Contents
- applications
- features
- key specifications
- table of contents
- list of figures
- list of tables
- 1 signal descriptions
- 2 system level description
- 3 block level description
- 4 image sensor core digital functions
- 4.1 mirror and flip
- 4.2 image windowing
- 4.3 test pattern
- 4.4 50/60Hz detection
- 4.5 AEC and AGC algorithms
- 4.6 AEC/AGC steps
- 4.7 black level calibration (BLC)
- 4.8 strobe flash and frame exposure
- 4.9 xenon flash control
- 4.10 frame exposure (FREX) mode
- 4.11 FREX strobe flash control
- 4.12 one-time programmable (OTP) memory
- 5 image sensor processor digital functions
- 6 image sensor output interface digital functions
- 7 register tables
- table 7-1 system control registers (sheet 1 of 5)
- table 7-2 SCCB registers (sheet 1 of 2)
- table 7-3 group hold control registers
- table 7-4 AEC/AGC 1 registers
- table 7-5 system timing registers (sheet 1 of 3)
- table 7-6 AEC/AGC 2 registers (sheet 1 of 3)
- table 7-7 STROBE/frame exposure control registers (sheet 1 of 2)
- table 7-8 50/60 HZ DETECTION registers
- table 7-9 OTP control registers (sheet 1 of 2)
- table 7-10 BLC registers (sheet 1 of 3)
- table 7-11 frame control registers
- table 7-12 DVP registers (sheet 1 of 2)
- table 7-13 MIPI top registers (sheet 1 of 11)
- table 7-14 ISPFC registers
- table 7-15 ISP TOP control registers (sheet 1 of 6)
- table 7-16 AWB registers (sheet 1 of 3)
- table 7-17 average registers (sheet 1 of 2)
- table 7-18 DPC registers
- table 7-19 LENC registers (sheet 1 of 4)
- table 7-20 cluster DPC registers (sheet 1 of 2)
- table 7-21 windows registers
- table 7-22 AEC/AGC 3 registers
- 8 operating specifications
- 9 mechanical specifications
- 10 optical specifications
- revision history
Confidential for truly Only
color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology
OV5647
proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.0
0x300F
SC_CMMN_PAD_
SEL1
0x00 RW Bit[7:0]: io_y_sel[7:0]
0x3010
SC_CMMN_PAD_
SEL2
0x00 RW
Bit[7]: io_vsync_sel
Bit[6]: io_href_sel
Bit[5]: io_pclk_sel
Bit[4]: io_frex_sel
Bit[3]: io_strobe_sel
Bit[2]: io_sda_sel
Bit[1]: io_gpio1_sel
Bit[0]: io_gpio0_sel
0x3011 SC_CMMN_PAD_PK 0x02 RW
Bit[7]: pd_dato_en
Bit[6:5]: iP2X3v[3:2]
Bit[1]: frex_enb
0: Enable
1: Disable
0x3013
SC_CMMN_A_PWC_
PK_O
0x00 RW
Bit[7:4]: Debug control
Changing these registers is not
recommended
Bit[3]: bp_regulator
0: Enable internal regulator
1: Disable internal regulator
Bit[2:0]: Debug control
Changing these registers is not
recommended
0x3014
SC_CMMN_A_PWC_
PK_O
0x0B RW
Bit[6:4]: apd[2:0]
Bit[3:0]: DIO
0x3016
SC_CMMN_MIPI_
PHY
0x00 RW
Bit[7:6]: LPH
Bit[3]: mipi_pad_enable
Bit[2]: pgm_bp_hs_en_lat
btpass the latch of hs_enable
Bit[1:0]: ictl[1:0]
Bias current adjustment
0x3017
SC_CMMN_MIPI_
PHY
0x10 RW
Bit[7:6]: pgm_vcm[1:0]
High speed common mode
voltage
Bit[5:4]: pgm_lptx[1:0]
01: Driving strength of low speed
transmitter
Bit[3]: IHALF
Bias current reduction
Bit[2]: pgm_vicd
CD input low voltage
Bit[1]: pgm_vih
CD input high voltage-dummy
Bit[0]: pgm_hs_valid
Valid delay-dummy
table 6-1 system control registers (sheet 2 of 4)
address
register name
default
value
R/W
description










