Datasheet
Table Of Contents
- applications
- features
- key specifications
- table of contents
- list of figures
- list of tables
- 1 signal descriptions
- 2 system level description
- 3 block level description
- 4 image sensor core digital functions
- 4.1 mirror and flip
- 4.2 image windowing
- 4.3 test pattern
- 4.4 50/60Hz detection
- 4.5 AEC and AGC algorithms
- 4.6 AEC/AGC steps
- 4.7 black level calibration (BLC)
- 4.8 strobe flash and frame exposure
- 4.9 xenon flash control
- 4.10 frame exposure (FREX) mode
- 4.11 FREX strobe flash control
- 4.12 one-time programmable (OTP) memory
- 5 image sensor processor digital functions
- 6 image sensor output interface digital functions
- 7 register tables
- table 7-1 system control registers (sheet 1 of 5)
- table 7-2 SCCB registers (sheet 1 of 2)
- table 7-3 group hold control registers
- table 7-4 AEC/AGC 1 registers
- table 7-5 system timing registers (sheet 1 of 3)
- table 7-6 AEC/AGC 2 registers (sheet 1 of 3)
- table 7-7 STROBE/frame exposure control registers (sheet 1 of 2)
- table 7-8 50/60 HZ DETECTION registers
- table 7-9 OTP control registers (sheet 1 of 2)
- table 7-10 BLC registers (sheet 1 of 3)
- table 7-11 frame control registers
- table 7-12 DVP registers (sheet 1 of 2)
- table 7-13 MIPI top registers (sheet 1 of 11)
- table 7-14 ISPFC registers
- table 7-15 ISP TOP control registers (sheet 1 of 6)
- table 7-16 AWB registers (sheet 1 of 3)
- table 7-17 average registers (sheet 1 of 2)
- table 7-18 DPC registers
- table 7-19 LENC registers (sheet 1 of 4)
- table 7-20 cluster DPC registers (sheet 1 of 2)
- table 7-21 windows registers
- table 7-22 AEC/AGC 3 registers
- 8 operating specifications
- 9 mechanical specifications
- 10 optical specifications
- revision history
Confidential for truly Only
color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology
OV5647
proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.0
5.5 post binning function
CFA image subsample will suffer zig_zag issues around slant edges and color shift for it is an non-uniform method in
physical coordinate. Post binning will map these pixels to their physically correct location.
0x518A
MANUAL BLUE GAIN
MSB
0x04 RW Bit[3:0]: blu_gain_man[11:8]
0x518B
MANUAL BLUE GAIN
LSB
0x00 RW Bit[7:0]: blu_gain_man[7:0]
0x518C RED GAIN LIMIT 0xF0 RW
Bit[7:4]: red_gain_up_limit
Bit[3:0]: red_gain_dn_limit
They are only the highest 4 bits of
limitation.
Max red gain is
{red_gan_up_limit,FF}
Min red gain is
{red_gain_dn_limit,00}
0x518D GREEN GAIN LIMIT 0xF0 RW
Bit[7:4]: green_gain_up_limit
Bit[3:0]: green_gain_dn_limit
They are only the highest 4 bits of
limitation.
Max green gain is
{green_gan_up_limit,FF}
Min green gain is
{green_gain_dn_limit,00}
0x518E BLUE GAIN LIMIT 0xF0 RW
Bit[7:4]: blue_gain_up_limit
Bit[3:0]: blue_gain_dn_limit
They are only the highest 4 bits of
limitation.
Max blue gain is
{blue_gan_up_limit,FF}
Min blue gain is
{blue_gain_dn_limit,00}
table 5-5 post binning control registers
address
register name
default
value
R/W
description
0x5003 ISP CTRL3 0x0A RW Bit[2]: bin_en
0x504B ISP CTRL75 0x30 RW
Bit[5]: h_en
Bit[4]: v_en
table 5-4 AWB control registers (sheet 3 of 3)
address
register name
default
value
R/W
description










