Datasheet
Table Of Contents
- applications
- features
- key specifications
- table of contents
- list of figures
- list of tables
- 1 signal descriptions
- 2 system level description
- 3 block level description
- 4 image sensor core digital functions
- 4.1 mirror and flip
- 4.2 image windowing
- 4.3 test pattern
- 4.4 50/60Hz detection
- 4.5 AEC and AGC algorithms
- 4.6 AEC/AGC steps
- 4.7 black level calibration (BLC)
- 4.8 strobe flash and frame exposure
- 4.9 xenon flash control
- 4.10 frame exposure (FREX) mode
- 4.11 FREX strobe flash control
- 4.12 one-time programmable (OTP) memory
- 5 image sensor processor digital functions
- 6 image sensor output interface digital functions
- 7 register tables
- table 7-1 system control registers (sheet 1 of 5)
- table 7-2 SCCB registers (sheet 1 of 2)
- table 7-3 group hold control registers
- table 7-4 AEC/AGC 1 registers
- table 7-5 system timing registers (sheet 1 of 3)
- table 7-6 AEC/AGC 2 registers (sheet 1 of 3)
- table 7-7 STROBE/frame exposure control registers (sheet 1 of 2)
- table 7-8 50/60 HZ DETECTION registers
- table 7-9 OTP control registers (sheet 1 of 2)
- table 7-10 BLC registers (sheet 1 of 3)
- table 7-11 frame control registers
- table 7-12 DVP registers (sheet 1 of 2)
- table 7-13 MIPI top registers (sheet 1 of 11)
- table 7-14 ISPFC registers
- table 7-15 ISP TOP control registers (sheet 1 of 6)
- table 7-16 AWB registers (sheet 1 of 3)
- table 7-17 average registers (sheet 1 of 2)
- table 7-18 DPC registers
- table 7-19 LENC registers (sheet 1 of 4)
- table 7-20 cluster DPC registers (sheet 1 of 2)
- table 7-21 windows registers
- table 7-22 AEC/AGC 3 registers
- 8 operating specifications
- 9 mechanical specifications
- 10 optical specifications
- revision history
Confidential for truly Only
11.03.2009 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies
2-5
figure 2-4 power up timing with external DVDD source
2.6 reset
Two reset modes are available for the OV5647:
• hardware reset
• SCCB software reset
The OV5647 sensor includes a RESETB pad that forces a complete hardware reset when it is pulled low (GND). The
OV5647 clears all registers and resets them to their default values when a hardware reset occurs. A reset can also be
initiated through the SCCB interface by setting register 0x0103[0] to high.
The whole chip will be reset during power up. Manually applying a hard reset upon power up is recommended even
though the on-chip power up reset is included. The hard reset is active low with an asynchronized design. The reset pulse
width should be greater than or equal to 1 ms.
2.7 standby and sleep
Two suspend modes are available for the OV5647:
• hardware standby
• SCCB software sleep
To initiate hardware standby mode, the PWDN pad must be tied to high. When this occurs, the OV5647 internal device
clock is halted and all internal counters are reset and registers are maintained. Executing a software sleep (0x0100[0])
through the SCCB interface suspends internal circuit activity but does not halt the device clock. All register content is
maintained in both modes.
VDD_IO
(DOVDD)
VDD_A
(AVDD)
VDD_D
(DVDD)
SCCB activity is okay during entire period
cut off power
VDD
_
IO first, then VDD_A, followed by VDD
_
D, and rising time is less than 5 ms
PWDN
SCCB
note T0 ≥ 0 ms: delay from VDD_IO stable to VDD_A stable
T1 ≥ 0 ms: delay from VDD_A stable to VDD_D stable
T2 ≥ 5 ms: delay from VDD_D stable to sensor power up stable
T0
T1
T2
power on period
5647_DS_2_4










