Datasheet

Confidential for truly Only
color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology
OV5647
proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.0
figure 2-3 power up timing with internal DVDD
2.5.2 power up with external DVDD source
For powering up with an external DVDD source and SCCB access during the power ON period, the following conditions
must occur:
1. if V
DD-IO
and V
DD-A
are turned ON at the same time, make sure V
DD-IO
becomes stable before V
DD-A
becomes stable
2. if V
DD-A
and V
DD-D
are turned ON at the same time, make sure V
DD-A
becomes stable before V
DD-D
becomes
stable
3. PWDN is active high with an asynchronized design (does not need clock)
4. for PWDN to go low, power must first become stable (DVDD to PWDN > 5 ms)
5. all powers are cut off when the camera is not in use (power down mode is not recommended
6. RESETB is active low with an asynchronized design
7. state of RESETB does not matter during power up period once DOVDD is up
8. master clock XVCLK should provide at least 1 ms before host accesses sensor’s SCCB
9. host can access SCCB bus (if shared) during entire period. 20 ms after PWDN goes low or 20 ms after
RESETB goes high if reset is inserted after PWDN goes high, host can access sensor’s SCCB to initialize
sensor
VDD_IO
(DOVDD)
VDD_A
(AVDD)
SCCB activity is okay during entire period
power down
VDD
_
IO first, then VDD_A, and rising time is less than 5 ms
PWDN
SCCB
note T0 ≥ 0 ms: delay from VDD_IO stable to VDD_A stable
T2 ≥ 5 ms: delay from VDD_A stable to sensor power up stable
T0
T2
power on period
5647_DS_2_3