Datasheet
Table Of Contents
- applications
- features
- key specifications
- table of contents
- list of figures
- list of tables
- 1 signal descriptions
- 2 system level description
- 3 block level description
- 4 image sensor core digital functions
- 4.1 mirror and flip
- 4.2 image windowing
- 4.3 test pattern
- 4.4 50/60Hz detection
- 4.5 AEC and AGC algorithms
- 4.6 AEC/AGC steps
- 4.7 black level calibration (BLC)
- 4.8 strobe flash and frame exposure
- 4.9 xenon flash control
- 4.10 frame exposure (FREX) mode
- 4.11 FREX strobe flash control
- 4.12 one-time programmable (OTP) memory
- 5 image sensor processor digital functions
- 6 image sensor output interface digital functions
- 7 register tables
- table 7-1 system control registers (sheet 1 of 5)
- table 7-2 SCCB registers (sheet 1 of 2)
- table 7-3 group hold control registers
- table 7-4 AEC/AGC 1 registers
- table 7-5 system timing registers (sheet 1 of 3)
- table 7-6 AEC/AGC 2 registers (sheet 1 of 3)
- table 7-7 STROBE/frame exposure control registers (sheet 1 of 2)
- table 7-8 50/60 HZ DETECTION registers
- table 7-9 OTP control registers (sheet 1 of 2)
- table 7-10 BLC registers (sheet 1 of 3)
- table 7-11 frame control registers
- table 7-12 DVP registers (sheet 1 of 2)
- table 7-13 MIPI top registers (sheet 1 of 11)
- table 7-14 ISPFC registers
- table 7-15 ISP TOP control registers (sheet 1 of 6)
- table 7-16 AWB registers (sheet 1 of 3)
- table 7-17 average registers (sheet 1 of 2)
- table 7-18 DPC registers
- table 7-19 LENC registers (sheet 1 of 4)
- table 7-20 cluster DPC registers (sheet 1 of 2)
- table 7-21 windows registers
- table 7-22 AEC/AGC 3 registers
- 8 operating specifications
- 9 mechanical specifications
- 10 optical specifications
- revision history
Confidential for truly Only
color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology
OV5647
proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.0
8.3 DC characteristics
table 8-3 DC characteristics (-30°C < T
A
< 70°C)
symbol parameter min typ max unit
supply
V
DD-A
supply voltage (analog) 2.6 2.8 3.0 V
V
DD-DO
supply voltage (digital I/O) 1.7 1.8 3.0 V
V
DD-D
supply voltage (digital core)
a
a. when internal regulator is bypassed
1.425 1.5 1.575 V
V
DD-E
supply voltage (MIPI) 1.425 1.5 1.575 V
I
DD-A
active (operating) current
2592 x 1944 @ 15 fps
b
b. using internal regulator for DVDD and short DVDD with EVDD; DOVDD = 2.8V. The currents are for DVP output.
MIPI output will results 5%-10% lower active current on I
DD-DO
TBD TBD mA
I
DD-DO
TBD TBD mA
I
DD-A
active (operating) current
720p @ 30fps
TBD TBD mA
I
DD-DO
TBD TBD mA
I
DD-A
active (operating) current
720p @ 60fps
TBD TBD mA
I
DD-DO
TBD TBD mA
I
DD-A
active (operating) current
VGA @ 30fps
TBD TBD mA
I
DD-DO
TBD TBD mA
I
DD-A
active (operating) current
VGA @ 60fps
TBD TBD mA
I
DD-DO
TBD TBD mA
I
DDS-SCCB
c
c. external clock is stopped during measurement
standby current
TBD TBD µA
I
DDS-PWDN
TBD TBD µA
digital inputs (typical conditions: AVDD = 2.8V, DVDD = 1.5V, DOVDD = 1.8V)
V
IL
input voltage LOW 0.54 V
V
IH
input voltage HIGH 1.26 V
C
IN
input capacitor 10 pF
digital outputs (standard loading 25 pF)
V
OH
output voltage HIGH 1.62 V
V
OL
output voltage LOW 0.18 V
serial interface inputs
V
IL
d
d. based on DOVDD = 1.8V
SCL and SDA -0.5 0 0.54 V
V
IH
d
SCL and SDA 1.26 1.8 2.3 V










