Datasheet
Table Of Contents
- applications
- features
- key specifications
- table of contents
- list of figures
- list of tables
- 1 signal descriptions
- 2 system level description
- 3 block level description
- 4 image sensor core digital functions
- 4.1 mirror and flip
- 4.2 image windowing
- 4.3 test pattern
- 4.4 50/60Hz detection
- 4.5 AEC and AGC algorithms
- 4.6 AEC/AGC steps
- 4.7 black level calibration (BLC)
- 4.8 strobe flash and frame exposure
- 4.9 xenon flash control
- 4.10 frame exposure (FREX) mode
- 4.11 FREX strobe flash control
- 4.12 one-time programmable (OTP) memory
- 5 image sensor processor digital functions
- 6 image sensor output interface digital functions
- 7 register tables
- table 7-1 system control registers (sheet 1 of 5)
- table 7-2 SCCB registers (sheet 1 of 2)
- table 7-3 group hold control registers
- table 7-4 AEC/AGC 1 registers
- table 7-5 system timing registers (sheet 1 of 3)
- table 7-6 AEC/AGC 2 registers (sheet 1 of 3)
- table 7-7 STROBE/frame exposure control registers (sheet 1 of 2)
- table 7-8 50/60 HZ DETECTION registers
- table 7-9 OTP control registers (sheet 1 of 2)
- table 7-10 BLC registers (sheet 1 of 3)
- table 7-11 frame control registers
- table 7-12 DVP registers (sheet 1 of 2)
- table 7-13 MIPI top registers (sheet 1 of 11)
- table 7-14 ISPFC registers
- table 7-15 ISP TOP control registers (sheet 1 of 6)
- table 7-16 AWB registers (sheet 1 of 3)
- table 7-17 average registers (sheet 1 of 2)
- table 7-18 DPC registers
- table 7-19 LENC registers (sheet 1 of 4)
- table 7-20 cluster DPC registers (sheet 1 of 2)
- table 7-21 windows registers
- table 7-22 AEC/AGC 3 registers
- 8 operating specifications
- 9 mechanical specifications
- 10 optical specifications
- revision history
Confidential for truly Only
11.03.2009 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies
7-47
0x5907 OTP CTRL07 0x38 RW
Bit[7]: Not used
Bit[6:4]: remain_bit
Bit[3:0]: Threshold
0x5908
OTP MAN X EVEN
INC
0x01 RW
Bit[7:4]: Not used
Bit[3:0]: otp_man_x_even_inc
0x5909 OTP MAN X ODD INC 0x01 RW
Bit[7:4]: Not used
Bit[3:0]: otp_man_x_odd_inc
0x590A
OTP MAN Y EVEN
INC
0x01 RW
Bit[7:4]: Not used
Bit[3:0]: otp_man_y_even_inc
0x590B OTP MAN Y ODD INC 0x01 RW
Bit[7:4]: Not used
Bit[3:0]: otp_man_y_odd_inc
0x590C~
0x590D
DEBUG MODE – – Not Used
table 7-21 windows registers
address
register name
default
value
R/W
description
0x5980 WINDOW XSTART 0x00 RW
Bit[7:5]: Not used
Bit[4:0]: window_xstart[12:8]
0x5981 WINDOW XSTART 0x00 RW Bit[7:0]: window_xstart[7:0]
0x5982 WINDOW YSTART 0x00 RW
Bit[7:4]: Not used
Bit[3:0]: window_ystart[11:8]
0x5983 WINDOW YSTART 0x00 RW Bit[7:0]: window_ystart[7:0]
0x5984 WIN X WIN 0x10 RW
Bit[7:5]: Not used
Bit[4:0]: window_x_win[12:8]
0x5985 WIN X WIN 0xA0 RW Bit[7:0]: window_x_win[7:0]
0x5986 WIN Y WIN 0x0C RW
Bit[7:4]: Not used
Bit[3:0]: window_y_win[11:8]
0x5987 WIN Y WIN 0x78 RW Bit[7:0]: window_y_win[7:0]
0x5988 WIN MAN 0x00 RW
Bit[7:1]: Not used
Bit[0]: Window manual enable
0: Auto mode
1: Manual mode
table 7-20 cluster DPC registers (sheet 2 of 2)
address
register name
default
value
R/W
description