Datasheet
Table Of Contents
- applications
- features
- key specifications
- table of contents
- list of figures
- list of tables
- 1 signal descriptions
- 2 system level description
- 3 block level description
- 4 image sensor core digital functions
- 4.1 mirror and flip
- 4.2 image windowing
- 4.3 test pattern
- 4.4 50/60Hz detection
- 4.5 AEC and AGC algorithms
- 4.6 AEC/AGC steps
- 4.7 black level calibration (BLC)
- 4.8 strobe flash and frame exposure
- 4.9 xenon flash control
- 4.10 frame exposure (FREX) mode
- 4.11 FREX strobe flash control
- 4.12 one-time programmable (OTP) memory
- 5 image sensor processor digital functions
- 6 image sensor output interface digital functions
- 7 register tables
- table 7-1 system control registers (sheet 1 of 5)
- table 7-2 SCCB registers (sheet 1 of 2)
- table 7-3 group hold control registers
- table 7-4 AEC/AGC 1 registers
- table 7-5 system timing registers (sheet 1 of 3)
- table 7-6 AEC/AGC 2 registers (sheet 1 of 3)
- table 7-7 STROBE/frame exposure control registers (sheet 1 of 2)
- table 7-8 50/60 HZ DETECTION registers
- table 7-9 OTP control registers (sheet 1 of 2)
- table 7-10 BLC registers (sheet 1 of 3)
- table 7-11 frame control registers
- table 7-12 DVP registers (sheet 1 of 2)
- table 7-13 MIPI top registers (sheet 1 of 11)
- table 7-14 ISPFC registers
- table 7-15 ISP TOP control registers (sheet 1 of 6)
- table 7-16 AWB registers (sheet 1 of 3)
- table 7-17 average registers (sheet 1 of 2)
- table 7-18 DPC registers
- table 7-19 LENC registers (sheet 1 of 4)
- table 7-20 cluster DPC registers (sheet 1 of 2)
- table 7-21 windows registers
- table 7-22 AEC/AGC 3 registers
- 8 operating specifications
- 9 mechanical specifications
- 10 optical specifications
- revision history
Confidential for truly Only
color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology
OV5647
proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.0
0x5838 BRMATRX40 0xAA RW
Bit[7:4]: blue_matrix_40
Bit[3:0]: red_matrix_40
0x5839 BRMATRX41 0xAA RW
Bit[7:4]: blue_matrix_41
Bit[3:0]: red_matrix_41
0x583A BRMATRX42 0xAA RW
Bit[7:4]: blue_matrix_42
Bit[3:0]: red_matrix_42
0x583B BRMATRX43 0xAA RW
Bit[7:4]: blue_matrix_43
Bit[3:0]: red_matrix_43
0x583C BRMATRX44 0xAA RW
Bit[7:4]: blue_matrix_44
Bit[3:0]: red_matrix_44
table 7-20 cluster DPC registers (sheet 1 of 2)
address
register name
default
value
R/W
description
0x5900 OTP START ADDR 0x10 RW
Bit[7:6]: Not used
Bit[5:0]: otp_start_addr
0x5901 OTP END ADDR 0x1F RW
Bit[7:6]: Not used
Bit[5:0]: otp_end_addr
0x5902 OTP CTRL02 0x00 RW
Bit[7:5]: Not used
Bit[4]: man_inc_en
Bit[3]: disable_mf
Bit[2]: disable_offset
Bit[1]: mirror_opt
Bit[0]: disable_bin
0x5903 OTP CTRL03 0x6F RW
Bit[7]: Not used
Bit[6:5]: recov_method
Bit[4]: fixed_replace
Bit[3]: fixed_ptn
Bit[2]: flip_opt
Bit[1]: expo_en
Bit[0]: gain_en
0x5904 EXPO CONS 0x00 RW
Bit[7]: Not used
Bit[6:0]: otp_expo_constrain
0x5905 EXPO CONS 0x00 RW Bit[7:0]: otp_expo_constrain
0x5906 GAIN CONS 0x07 RW
Bit[7:6]: Not used
Bit[5:0]: otp_expo_constrain
table 7-19 LENC registers (sheet 4 of 4)
address
register name
default
value
R/W
description










