Datasheet
Table Of Contents
- applications
- features
- key specifications
- table of contents
- list of figures
- list of tables
- 1 signal descriptions
- 2 system level description
- 3 block level description
- 4 image sensor core digital functions
- 4.1 mirror and flip
- 4.2 image windowing
- 4.3 test pattern
- 4.4 50/60Hz detection
- 4.5 AEC and AGC algorithms
- 4.6 AEC/AGC steps
- 4.7 black level calibration (BLC)
- 4.8 strobe flash and frame exposure
- 4.9 xenon flash control
- 4.10 frame exposure (FREX) mode
- 4.11 FREX strobe flash control
- 4.12 one-time programmable (OTP) memory
- 5 image sensor processor digital functions
- 6 image sensor output interface digital functions
- 7 register tables
- table 7-1 system control registers (sheet 1 of 5)
- table 7-2 SCCB registers (sheet 1 of 2)
- table 7-3 group hold control registers
- table 7-4 AEC/AGC 1 registers
- table 7-5 system timing registers (sheet 1 of 3)
- table 7-6 AEC/AGC 2 registers (sheet 1 of 3)
- table 7-7 STROBE/frame exposure control registers (sheet 1 of 2)
- table 7-8 50/60 HZ DETECTION registers
- table 7-9 OTP control registers (sheet 1 of 2)
- table 7-10 BLC registers (sheet 1 of 3)
- table 7-11 frame control registers
- table 7-12 DVP registers (sheet 1 of 2)
- table 7-13 MIPI top registers (sheet 1 of 11)
- table 7-14 ISPFC registers
- table 7-15 ISP TOP control registers (sheet 1 of 6)
- table 7-16 AWB registers (sheet 1 of 3)
- table 7-17 average registers (sheet 1 of 2)
- table 7-18 DPC registers
- table 7-19 LENC registers (sheet 1 of 4)
- table 7-20 cluster DPC registers (sheet 1 of 2)
- table 7-21 windows registers
- table 7-22 AEC/AGC 3 registers
- 8 operating specifications
- 9 mechanical specifications
- 10 optical specifications
- revision history
Confidential for truly Only
11.03.2009 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies
7-39
0x5057 ISP CTRL57 0x00 RW
Bit[7]: sram_test_dpc1
Bit[6]: sram_test_dpc2
Bit[5]: sram_test_dpc3
Bit[4]: sram_test_dpc4
Bit[3:0]: Not used
0x5058 ISP CTRL58 0xAA RW
Bit[7:4]: sram_rm_dpc1
Bit[3:0]: sram_rm_dpc2
0x5059 ISP CTRL59 0xAA RW
Bit[7:4]: sram_rm_dpc3
Bit[3:0]: sram_rm_dpc4
table 7-16 AWB registers (sheet 1 of 3)
address
register name
default
value
R/W
description
0x5180 AWB CTRL 0x00 RW
Bit[7]: hsize_man_en
Bit[6]: fast_awb
0: Disable fast AWB
calculation function
1: Enable fast AWB
calculation function
Bit[5]: freeze_gain_en
When it is enabled, the output
AWB gains are input AWB
gains
Bit[4]: freeze_sum_en
When it is set, the sums and
averages value are the same
as previous frame
Bit[3]: gain_man_en
0: Output calculated gains
1: Output manual gains set
by registers
Bit[2]: start_sel
0: Select the last href
falling edge of before
gain input as cal start
signal
1: Select the last href
falling edge of after gain
input as cal start signal
Bit[1]: after_gma
Bit[0]: Not used
table 7-15 ISP TOP control registers (sheet 6 of 6)
address
register name
default
value
R/W
description










