Datasheet
Table Of Contents
- applications
- features
- key specifications
- table of contents
- list of figures
- list of tables
- 1 signal descriptions
- 2 system level description
- 3 block level description
- 4 image sensor core digital functions
- 4.1 mirror and flip
- 4.2 image windowing
- 4.3 test pattern
- 4.4 50/60Hz detection
- 4.5 AEC and AGC algorithms
- 4.6 AEC/AGC steps
- 4.7 black level calibration (BLC)
- 4.8 strobe flash and frame exposure
- 4.9 xenon flash control
- 4.10 frame exposure (FREX) mode
- 4.11 FREX strobe flash control
- 4.12 one-time programmable (OTP) memory
- 5 image sensor processor digital functions
- 6 image sensor output interface digital functions
- 7 register tables
- table 7-1 system control registers (sheet 1 of 5)
- table 7-2 SCCB registers (sheet 1 of 2)
- table 7-3 group hold control registers
- table 7-4 AEC/AGC 1 registers
- table 7-5 system timing registers (sheet 1 of 3)
- table 7-6 AEC/AGC 2 registers (sheet 1 of 3)
- table 7-7 STROBE/frame exposure control registers (sheet 1 of 2)
- table 7-8 50/60 HZ DETECTION registers
- table 7-9 OTP control registers (sheet 1 of 2)
- table 7-10 BLC registers (sheet 1 of 3)
- table 7-11 frame control registers
- table 7-12 DVP registers (sheet 1 of 2)
- table 7-13 MIPI top registers (sheet 1 of 11)
- table 7-14 ISPFC registers
- table 7-15 ISP TOP control registers (sheet 1 of 6)
- table 7-16 AWB registers (sheet 1 of 3)
- table 7-17 average registers (sheet 1 of 2)
- table 7-18 DPC registers
- table 7-19 LENC registers (sheet 1 of 4)
- table 7-20 cluster DPC registers (sheet 1 of 2)
- table 7-21 windows registers
- table 7-22 AEC/AGC 3 registers
- 8 operating specifications
- 9 mechanical specifications
- 10 optical specifications
- revision history
Confidential for truly Only
color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology
OV5647
proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.0
0x503E ISP CTRL3E 0x00 RW
Bit[7]: Not used
Bit[6]: win_cut_en
Bit[5]: isp_test
0: Two lowest bits are 1
1: Two lowest bits are 0
Bit[4]: Two lowest bits are rnd_same
0: Frame-changing random data
pattern
1: Frame-fixed random data
pattern
Bit[3:0]: rnd_seed
Initial seed for random data pattern
0x504B ISP CTRL4B 0x30 RW
ISP Control
(0: disable ISP; 1: enable ISP)
Bit[7:6]: Not used
Bit[5]: post_binning h_enable
Bit[4]: post_binning v_enable
Bit[3]: flip_man_en
Bit[2]: flip_man
Bit[1]: mirror_man_en
Bit[0]: Mirror
0x504C ISP CTRL4C 0x04 RW Bit[7:0]: bias_man
0x504D ISP CTRL4D 0x00 RW
ISP Control
(0: Disable ISP; 1: Enable ISP)
Bit[7:4]: Not used
Bit[3]: lenc_xoff_man_en
Bit[2]: lenc_yoff_man_en
Bit[1]: lenc_gain_man_en
Bit[0]: lenc_bias_man_en
0x504E ISP CTRL4E 0x04 RW
Bit[7:4]: Not used
Bit[3:0]: lenc_xoff_man[11:8]
0x504F ISP CTRL4F 0x00 RW Bit[7:0]: lenc_xoff_man[7:0]
0x5052 ISP CTRL52 0x0A RW
Bit[7:4]: Not used
Bit[3:0]: lenc_yoff_man[11:8]
0x5053 ISP CTRL53 0x00 RW Bit[7:0]: lenc_yoff_man[7:0]
0x5054 ISP CTRL54 0x00 RW
Bit[7:2]: Not used
Bit[1:0]: lenc_gain_man[9:8]
0x5055 ISP CTRL55 0x00 RW Bit[7:0]: lenc_gain_man[7:0]
0x5056 ISP CTRL56 0x00 RW
Bit[7:6]: Not used
Bit[5]: lenc_skipx_man
Bit[4]: lenc_skipy_man
Bit[3:2]: lenc_skipy_man
Bit[1:0]: lenc_skipx_man
table 7-15 ISP TOP control registers (sheet 5 of 6)
address
register name
default
value
R/W
description