Datasheet
Table Of Contents
- applications
- features
- key specifications
- table of contents
- list of figures
- list of tables
- 1 signal descriptions
- 2 system level description
- 3 block level description
- 4 image sensor core digital functions
- 4.1 mirror and flip
- 4.2 image windowing
- 4.3 test pattern
- 4.4 50/60Hz detection
- 4.5 AEC and AGC algorithms
- 4.6 AEC/AGC steps
- 4.7 black level calibration (BLC)
- 4.8 strobe flash and frame exposure
- 4.9 xenon flash control
- 4.10 frame exposure (FREX) mode
- 4.11 FREX strobe flash control
- 4.12 one-time programmable (OTP) memory
- 5 image sensor processor digital functions
- 6 image sensor output interface digital functions
- 7 register tables
- table 7-1 system control registers (sheet 1 of 5)
- table 7-2 SCCB registers (sheet 1 of 2)
- table 7-3 group hold control registers
- table 7-4 AEC/AGC 1 registers
- table 7-5 system timing registers (sheet 1 of 3)
- table 7-6 AEC/AGC 2 registers (sheet 1 of 3)
- table 7-7 STROBE/frame exposure control registers (sheet 1 of 2)
- table 7-8 50/60 HZ DETECTION registers
- table 7-9 OTP control registers (sheet 1 of 2)
- table 7-10 BLC registers (sheet 1 of 3)
- table 7-11 frame control registers
- table 7-12 DVP registers (sheet 1 of 2)
- table 7-13 MIPI top registers (sheet 1 of 11)
- table 7-14 ISPFC registers
- table 7-15 ISP TOP control registers (sheet 1 of 6)
- table 7-16 AWB registers (sheet 1 of 3)
- table 7-17 average registers (sheet 1 of 2)
- table 7-18 DPC registers
- table 7-19 LENC registers (sheet 1 of 4)
- table 7-20 cluster DPC registers (sheet 1 of 2)
- table 7-21 windows registers
- table 7-22 AEC/AGC 3 registers
- 8 operating specifications
- 9 mechanical specifications
- 10 optical specifications
- revision history
Confidential for truly Only
11.03.2009 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies
7-35
0x5005 ISP CTRL05 0x31 RW
Bit[7]: sof_man
0: SOF from BLC module
1: SOF from pre_isp module
Bit[6]: awb_bias_man_en
0: AWB bias manual disable
1: AWB bias manual enable
Bit[5]: awb_bias_on
0: Disable AWB bias
1: Enable AWB bias
Bit[4:3]: Not used
Bit[2]: lenc_bias_on
0: Disable LENC bias
1: Enable LENC bias
Bit[1]: Disable LENC bias
s2p_sw_en_o
Bit[0]: Disable LENC bias avg_en
0: Disable
1: Enable
0x5006 ISP CTRL06 0x00 RW
ISP Control
(0: disable ISP; 1: enable ISP)
Bit[7]: x_odd_inc_man_en
Bit[6]: y_even_inc_man_en
Bit[5]: x_odd_inc_man_en
Bit[4]: y_even_inc_man_en
Bit[3]: x_offset_man_en
Bit[2]: y_offset_man_en
Bit[1]: x_skip_man_en
Bit[0]: y_skip_man_en
0x5007 ISP CTRL07 0x00 RW
ISP Control
(0: disable ISP; 1: enable ISP)
Bit[7]: bin_mode_man_en
Bit[6]: bin_mode_man
Bit[5]: win_x_off_man_en
Bit[4]: win_y_off_man_en
Bit[3]: win_x_out_man_en
Bit[2]: win_y_out_man_en
Bit[1]: isp_input_h_man_en
Bit[0]: isp_input_v_man_en
0x5008 X OFFSET MAN 0x00 RW
Bit[7:4]: Not used
Bit[3:0]: x_offset_man[11:8]
0x5009 X OFFSET MAN 0x00 RW Bit[7:0]: x_offset_man[7:0]
0x500A Y OFFSET MAN 0x00 RW
Bit[7:3]: Not used
Bit[2:0]: y_offset_man[10:8]
0x500B Y OFFSET MAN 0x00 RW Bit[7:0]: y_offset_man[7:0]
table 7-15 ISP TOP control registers (sheet 2 of 6)
address
register name
default
value
R/W
description










