Datasheet

Confidential for truly Only
11.03.2009 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies
7-33
0x4865 MIPI_ST – R
Bit[7:6]: Not used
Bit[5]: lp_rx_sel_i
0: Not used
1: MIPI_LP_RX receives LP data
Bit[4]: tx_busy_i
0: Not used
1: MIPI_TX_LP_TX is busy to send
LP data
Bit[3]: mipi_lp_p1_i
MIPI low power input for lane 1p
Bit[2]: mipi_lp_n1_i
MIPI low power input for lane 1n
Bit[1]: mipi_lp_p2_i
MIPI low power input for lane 2p
Bit[0]: mipi_lp_n2_i
MIPI low power input for lane 2n
0x4866 T_GLB_TIM_H – R
Bit[7]: VHREF ahead of flag, must delay vhref
Bit[6:0]: vhref_delay_h
0x4867 T_GLB_TIM_L – R vhref_delay_l
table 7-14 ISPFC registers
address register name
default
value R/W description
0x4900 FRAME CTRL0 0x00 RW
Bit[7:3]: Not used
Bit[2]: fcnt_eof_sel
Bit[1]: fcnt_mask_dis
Bit[0]: fcnt_reset
0x4901 FRAME ON NUMBER 0x00 RW
Bit[7:3]: Not used
Bit[3:0]: Frame ON number
0x4902
FRAME OFF
NUMBER
0x00 RW
Bit[7:3]: Not used
Bit[3:0]: Frame OFF number
0x4903 FRAME CTRL1 0x00 RW
Bit[7:6]: Not used
Bit[5]: data_mask_dis
Bit[4]: valid_mask_dis
Bit[3]: href_mask_dis
Bit[2]: eof_mask_dis
Bit[1]: sof_mask_dis
Bit[0]: all_mask_dis
table 7-13 MIPI top registers (sheet 11 of 11)
address register name
default
value R/W description