Datasheet
Table Of Contents
- applications
- features
- key specifications
- table of contents
- list of figures
- list of tables
- 1 signal descriptions
- 2 system level description
- 3 block level description
- 4 image sensor core digital functions
- 4.1 mirror and flip
- 4.2 image windowing
- 4.3 test pattern
- 4.4 50/60Hz detection
- 4.5 AEC and AGC algorithms
- 4.6 AEC/AGC steps
- 4.7 black level calibration (BLC)
- 4.8 strobe flash and frame exposure
- 4.9 xenon flash control
- 4.10 frame exposure (FREX) mode
- 4.11 FREX strobe flash control
- 4.12 one-time programmable (OTP) memory
- 5 image sensor processor digital functions
- 6 image sensor output interface digital functions
- 7 register tables
- table 7-1 system control registers (sheet 1 of 5)
- table 7-2 SCCB registers (sheet 1 of 2)
- table 7-3 group hold control registers
- table 7-4 AEC/AGC 1 registers
- table 7-5 system timing registers (sheet 1 of 3)
- table 7-6 AEC/AGC 2 registers (sheet 1 of 3)
- table 7-7 STROBE/frame exposure control registers (sheet 1 of 2)
- table 7-8 50/60 HZ DETECTION registers
- table 7-9 OTP control registers (sheet 1 of 2)
- table 7-10 BLC registers (sheet 1 of 3)
- table 7-11 frame control registers
- table 7-12 DVP registers (sheet 1 of 2)
- table 7-13 MIPI top registers (sheet 1 of 11)
- table 7-14 ISPFC registers
- table 7-15 ISP TOP control registers (sheet 1 of 6)
- table 7-16 AWB registers (sheet 1 of 3)
- table 7-17 average registers (sheet 1 of 2)
- table 7-18 DPC registers
- table 7-19 LENC registers (sheet 1 of 4)
- table 7-20 cluster DPC registers (sheet 1 of 2)
- table 7-21 windows registers
- table 7-22 AEC/AGC 3 registers
- 8 operating specifications
- 9 mechanical specifications
- 10 optical specifications
- revision history
Confidential for truly Only
color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology
OV5647
proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.0
0x483B MIPI_LP_GPIO 0x33 RW
Bit[7]: lp_sel1
0: Generate mipi_lp_dir1_o
automatically
1: Use lp_dir_man1 as
mipi_lp_dir1_o
Bit[6]: lp_dir_man1
0: Input
1: Output
Bit[5]: lp_p1_o
Bit[4]: lp_n1_o
Bit[3]: lp_sel2
0: Generate mipi_lp_dir2_o
automatically
1: Use lp_dir_man2 as
mipi_lp_dir2_o
Bit[2]: lp_dir_man2
0: Input
1: Output
Bit[1]: lp_p2_o
Bit[0]: lp_n2_o
0x483C MIPI CTRL 33 0x4F RW
Bit[7:4]: t_lpx, unit: sclk cycles
Bit[3:0]: t_clk_pre, unit: sclk cycles
0x483D MIPI_T_TA_GO 0x10 RW
t_ta_go
Unit: SCLK cycles
0x483E MIPI_T_TA_SURE 0x06 RW
t_ta_sure
Unit: SCLK cycles
0x483F MIPI_T_TA_GET 0x14 RW
t_ta_get
Unit: SCLK cycles
0x4843 SNR_PCLK_DIV 0x00 RW
Bit[7:1]: Not used
Bit[0]: PCLK divider
0: PCLK/SCLK = 2
and pclk_div = 1
1: PCLK/SCLK = 1
and pclk_div = 1
0x4860 MIPI CTRL 60 – R
MIPI Read/Write only
Bit[7:1]: Not used
Bit[0]: mipi_dis_me
0: Enable MIPI read/write registers
1: Disable MIPI read/write registers
0x4861 HD_SK_REG0 – R MIPI Read/Write, SCCB and MCU Read Only
0x4862 HD_SK_REG1 – R MIPI Read/Write, SCCB and MCU Read Only
0x4863 HD_SK_REG2 – R MIPI Read/Write, SCCB and MCU Read Only
0x4864 HD_SK_REG3 – R MIPI Read/Write, SCCB and MCU Read Only
table 7-13 MIPI top registers (sheet 10 of 11)
address
register name
default
value
R/W
description










