Datasheet
Table Of Contents
- applications
- features
- key specifications
- table of contents
- list of figures
- list of tables
- 1 signal descriptions
- 2 system level description
- 3 block level description
- 4 image sensor core digital functions
- 4.1 mirror and flip
- 4.2 image windowing
- 4.3 test pattern
- 4.4 50/60Hz detection
- 4.5 AEC and AGC algorithms
- 4.6 AEC/AGC steps
- 4.7 black level calibration (BLC)
- 4.8 strobe flash and frame exposure
- 4.9 xenon flash control
- 4.10 frame exposure (FREX) mode
- 4.11 FREX strobe flash control
- 4.12 one-time programmable (OTP) memory
- 5 image sensor processor digital functions
- 6 image sensor output interface digital functions
- 7 register tables
- table 7-1 system control registers (sheet 1 of 5)
- table 7-2 SCCB registers (sheet 1 of 2)
- table 7-3 group hold control registers
- table 7-4 AEC/AGC 1 registers
- table 7-5 system timing registers (sheet 1 of 3)
- table 7-6 AEC/AGC 2 registers (sheet 1 of 3)
- table 7-7 STROBE/frame exposure control registers (sheet 1 of 2)
- table 7-8 50/60 HZ DETECTION registers
- table 7-9 OTP control registers (sheet 1 of 2)
- table 7-10 BLC registers (sheet 1 of 3)
- table 7-11 frame control registers
- table 7-12 DVP registers (sheet 1 of 2)
- table 7-13 MIPI top registers (sheet 1 of 11)
- table 7-14 ISPFC registers
- table 7-15 ISP TOP control registers (sheet 1 of 6)
- table 7-16 AWB registers (sheet 1 of 3)
- table 7-17 average registers (sheet 1 of 2)
- table 7-18 DPC registers
- table 7-19 LENC registers (sheet 1 of 4)
- table 7-20 cluster DPC registers (sheet 1 of 2)
- table 7-21 windows registers
- table 7-22 AEC/AGC 3 registers
- 8 operating specifications
- 9 mechanical specifications
- 10 optical specifications
- revision history
Confidential for truly Only
11.03.2009 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies
7-31
0x4827 HS_PREPARE_MIN 0x32 RW
Low byte of the minimum value for hs_prepare
hs_prepare_real = hs_prepare_min_o +
Tui*ui_hs_prepare_min_o
0x4828 HS_EXIT_MIN 0x00 RW
High byte of the minimum value for hs_exit, unit ns
Bit[7:2]: Not used
Bit[1:0]: hs_exit_min[9:8]
0x4829 HS_EXIT_MIN 0x64 RW
Low byte of the minimum value for hs_exit
hs_exit_real = hs_exit_min_o +
Tui*ui_hs_exit_min_o
0x482A UI_HS_ZERO_MIN 0x05 RW Minimum UI Value of hs_zero, unit UI
0x482B UI_HS_TRAIL_MIN 0x04 RW Minimum UI Value of hs_trail, unit UI
0x482C
UI_CLK_ZERO_
MIN
0x00 RW Minimum UI Value of clk_zero, unit UI
0x482D
UI_CLK_PREPARE
_MIN
0x00 RW Minimum UI Value of clk_prepare, unit UI
0x482E
UI_CLK_POST_
MIN
0x34 RW Minimum UI Value of clk_post, unit UI
0x482F
UI_CLK_TRAIL_
MIN
0x00 RW Minimum UI Value of clk_trail, unit UI
0x4830 UI_LPX_P_MIN 0x00 RW Minimum UI Value of lpx_p, unit UI
0x4831
UI_HS_PREPARE_
MIN
0x04 RW Minimum UI Value of hs_prepare, unit UI
0x4832 UI_HS_EXIT_MIN 0x00 RW Minimum UI Value of hs_exit, unit UI
0x4833 MIPI_REG_MIN 0x00 RW
MIPI register address, lower bound (high byte)
Address range of MIPI RW registers is from
mipi_reg_min to mipi_reg_max
0x4834 MIPI_REG_MIN 0x00 RW MIPI Register Address, lower bound (low byte)
0x4835 MIPI_REG_MAX 0xFF RW MIPI Register Address, upper bound (high byte)
0x4836 MIPI_REG_MAX 0xFF RW MIPI Register Address, upper bound (low byte)
0x4837 PCLK_PERIOD 0x15 RW Period of pclk2x, pclk_div = 1, and 1-bit decimal
0x4838 WKUP_DLY 0x02 RW Wakeup Delay for MIPI
0x483A DIR_DLY 0v08 RW Change LP Direction Delay/2 after LP11
table 7-13 MIPI top registers (sheet 9 of 11)
address
register name
default
value
R/W
description