Datasheet

Confidential for truly Only
11.03.2009 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies
7-29
0x4806 MIPI REG RW CTRL 0x28 RW
Bit[7]: Test mode
Bit[6]: mipi_test
Bit[5]: mipi_lp_op
0: Use new option to reduce
mipi_lptx_p
1: Not used
Bit[4]: two_lane_man_en
0: Not used
1: Use two_lane_man to manually
control two_lane_mode
Bit[3]: two_lane_man
Bit[2]: rst_rtn_en
0: Not used
1: Change to input to allow host RW
register after reset
Bit[1]: frame_end_en
0: Not used
1: After frame end packet, change to
input to allow host RW register
Bit[0]: line_end_en
0: Not used
1: After line end packet, change to
input to allow host RW register
0x480A MIPI BIT ORDER 0x00 RW
Bit[7:3]: Not used
Bit[2]: Bit order reverse
Bit[1:0]: Bit position adjustment
01: {D[7:0],D[9:8]}
10: {D[1:0],D[9:2]}
0x4810
MIPI MAX FRAME
COUNT
0xFF RW
High Byte of Max Frame Count of Frame Sync Short
Packet
0x4811
MIPI MAX FRAME
COUNT
0xFF RW
Low Byte of Max Frame Count of Frame Sync Short
Packet
0x4814 MIPI CTRL14 0x2A RW
MIPI Control 14
Bit[7:6]: Virtual channel of MIPI
Bit[5:0]: Data type in manual mode
0x4815 MIPI_DT_SPKT 0x00 RW
Bit[7]: Not used
Bit[6]: pclk_div
0: Use rising edge of mipi_pclk_o to
generate MIPI bus to PHY
1: Use falling edge of mipi_pclk_o to
generate MIPI bus to PHY
Bit[5:0]: Manual data type for short packet
0x4818 HS_ZERO_MIN 0x00 RW
High byte of the minimum value for hs_zero
Unit ns
table 7-13 MIPI top registers (sheet 7 of 11)
address register name
default
value R/W description