Datasheet

PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__4_REV5.fm - Rev. B 2/06 EN
56 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
IFP Registers, Page 2
Micron Confidential and Proprietary
17
0x11
11:0 0x0258
Spoof Frame Height
This register defines the height of the spoof frame used to output data captured in the output FIFO. The height
is equal to the number of assertions of LINE_VALID within one assertion of FRAME_VALID. The value stored in
this register is ignored if bit R13:2[5] is set.
18
0x12
15:0 0x0606
Spoof Frame Line Timing
7:0 0x6
Spoof LINE_VALID lead. The number of clocks before LINE_VALID is asserted in a spoof
frame. This must be a minimum value of “5.”
15:8 0x6
Spoof LINE_VALID trail. The number of clocks after LINE_VALID is de-asserted in a spoof
frame. This must be a minimum value of “5.”
29
0x1D
15:0 0
JPEG RAM Test Control Register
9:0 0
Tested SRAM address: This register defines the location in the seventeen 800 x 16 RAMs
that is being accessed by the host or microcontroller while testing the group of SRAMs. A
specified 16-bit location can be selected from 0 through 799. The address is automatically
incremented when R31:2 is written during SRAM test data Write or read during SRAM test
data read.
12:10 0
Test Y/C SRAM Register: Address the same set of 8 SRAMs (either for Y or for C), this
register setting identifies which of the 8 SRAMs is selected. 000 for SRAM1, 001 for SRAM2,
…, 111 for SRAM8.
13 0
Test Y/C SRAM Select Register: Select a bank of 8 SRAMs from luminance or from
chrominance. Y = 1, C = 0.
14 0
Test output buffer SRAM: Select to read output buffer SRAM and supersedes Y/C SRAMs. If
set, data from the output buffer RAM is selected to be read. During data WRITE, this has no
effect.
15 0
SRAM write enable. This bit is used in conjunction with the RAM selection register. When
this bit is set, the RAM specified in the selection register undergoes a test write cycle. Data
residing in the indirect data register R31:2 is loaded into all seventeen 800 x 16 SRAMS
simultaneously. Resetting the bit thereafter causes a test read cycle to be performed and
the data is read from the SRAMs and loaded back into R31:2. This bit is write_enable when
1; read_enable when 0. The READ and WRITE cycles occur when R31:2 is accessed.
30
0x1E
15:0 0
JPEG Indirect Access Control Register
10:0 0
Indirect access address register: This 11-bit register contains the address of the register or
memory to be accessed indirectly.
12:11 0
Unused.
13 0
Enable two-wire serial interface burst: When this bit is set, the two-wire serial interface
decoder operates in burst mode for the indirect data register (READ burst and WRITE
burst). The longest burst supported is 16 (128 READ or WRITE cycles).
14 0
Enable indirect writing: When set, data from the indirect data register is written to the
Indirect address location specified by [10:0] of this register except when auto-increment is
set. Reading the same address location when this bit is reset to “0.”
15 0
Address auto-increment: When this bit is set, the value in the indirect access address
register is automatically incremented after every read or write, to the J
PEG indirect access
data register. This feature is used to emulate a burst access to memory or registers being
accessed indirectly.
31
0x1F
15:0 0
JPEG Indirect Access Data Register
Writing to, and reading from this register, is equivalent to performing these operations on registers or memory
being indirectly accessed. When address auto-increment bit is set in JPEG indirect access control register, multiple
writes or reads from this register affect a burst data transfer. Data is written to or read from Indirect registers
(when TestSRAM REG 0x0[1] is set to “0”), or the 800 x 16 SRAMs (when TestSRAM is set to “1”).
Table 7: IFP Registers, Page 2 (continued)
Reg # Bits Default Name