Datasheet

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MT9D111__4_REV5.fm - Rev. B 2/06 EN
55 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
IFP Registers, Page 2
Micron Confidential and Proprietary
80
Duplicate FRAME_VALID on LINE_VALID: When this bit is set, the FRAME_VALID waveform
is output on LINE_VALID output also; therefore, the two are identical.
90
Enable status insertion: When this bit is set, the JPEG module appends the status byte to
the end of the JPEG byte stream. This register should only be set when transferring in
continuous mode. The status byte inserted at the end of the JPEG byte stream is Reg2 bit
[7:0].
10 0
Enable spoof ITU-R BT.601 codes: This bit is relevant matters when uncompressed frames
are output in the spoof mode. When set, the bit causes the ITU-R BT.601 markers SOF, EOF,
SOL, EOL to be inserted into every frame. Codes are:
Start of Frame: FF0000AB
End of Frame: FF0000B6
Start of Line: FF000080
End of Line: FF00009D
11 0
Freeze_update; Default = 0.
When set, it disables the transfer of values from registers 0x0A, 0x0D (except
freeze_update), 0x0E, 0x0F, 0x10, 0x11, 0x12 into their corresponding shadow registers.
When cleared, the shadow registers are updated with values from their corresponding
configuration registers at the end of vertical blanking of the input image. The shadow
registers allow the microcontroller to change configuration registers values during the
active frame time without corrupting the current frame transfer.
14
0x0E
15:0 0x0501
Output PCLK1 & PCLK2 Configuration Register
3:0 0x1
Output clock frequency divisor N1: This 4-bit register contains an integer divisor used to
divide master clock frequency to obtain the frequency of output clock source PCLK1. A
value of “0” in this register has the same effect as “1.”
7:5 0
PCLK1 slew rate: The value contained in this 3-bit register determines the slew rate of the
output clock when PCLK1 is selected as its source.
11:8 0x5
Output Clock Frequency Divisor N2: This 4-bit register contains an integer divisor used to
divide master clock frequency to obtain the frequency of output clock source PCLK2. The
output clock switches from PCLK1 to PCLK2 when the output buffer fullness reaches 50%.
A value of “0” in this register has the same effect as “1.”
12 0
Not used.
15:13 0
PCLK2 slew rate: The value contained in this 3-bit register determines the slew rate of the
output clock when PCLK2 is selected as its source.
15
0x0F
7:0 0x0003
Output PCLK3 Configuration Register
3:0 0x03
Output clock frequency divisor N3: This 4-bit register contains an integer divisor used to
divide master clock frequency to obtain the frequency of output clock source PCLK3. The
output clock switches from PCLK2 to PCLK3 when the output buffer fullness reaches 75 %.
A value of “0” in this register has the same effect as 1.
40
Not used.
7:5 0
PCLK3 slew rate: The value contained in this 3-bit register determines the slew rate of the
output clock when PCLK3 is selected as its source.
16
0x10
11:0 0x0640
Spoof Frame Width
This register defines the width of the spoof frame used to output data captured in the output FIFO. It
corresponds to the number of valid data bytes output at each assertion of LINE_VALID. It must be an even
number.
Table 7: IFP Registers, Page 2 (continued)
Reg # Bits Default Name