Datasheet

PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__4_REV5.fm - Rev. B 2/06 EN
54 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
IFP Registers, Page 2
Micron Confidential and Proprietary
13
0x0D
10:0 0x0007
Output Configuration Register
01
Enable spoof frame: When this bit is set, the data captured in the output FIFO is sent out as
a spoofed frame, formatted according to information stored in the various spoof registers.
This output mode can be used to output both JPEG-compressed and uncompressed image
data. JPEG data may be padded if dummy data is needed. During LINE_VALID assertion
period, the output clock is only clocked when there is valid JPEG data or padded dummy
data to be transmitted. This may result in a non-uniform clock period. When LINE_VALID is
de-asserted, the output clock is enabled according to SPOOF_LV_LEAD and
SPOOF_LV_TRAIL setting. JPEG SOI/EOI markers cannot be inserted into spoof frames.
11
Enable output pixel clock between frames: When set, this bit enables the pixel clock to run
whether FRAME_VALID is LOW or HIGH. Clearing the bit disables the clock during the
periods when FRAME_VALID is de-asserted except for SOI/EOI markers transmission if they
are outside the FV assertion period. The gating off of this output pixel clock saves power.
21
Enable pixel clock during invalid data: When this bit is set, the pixel clock runs continuously
while FRAME_VALID is asserted but LINE_VALID is de-asserted. When cleared, it causes the
pixel clock to be active only when valid JPEG data are output. Disabling pixel clock during
LINE_VALID de-assertion is not support in spoof frame.
30
Enable SOI/EOI insertion: When set, this bit causes SOI and EOI markers to be output at the
beginning and end of every JPEG-encoded frame. When the bit is cleared, only JPEG data
bytes are output.
40
Insert SOI and EOI when FRAME_VALID is HIGH: When it is “1,” SOI and EOI are inside FV
assertion period. When it is”0,” SOI, and EOI are outside FRAME_VALID assertion period.
This bit is relevant only when SOI/EOI insertion is enabled.
50
Ignore spoof frame height: This bit is used in conjunction with bit 0 that enables spoof
framing. When this bit is set, the JPEG unit output section ignores the spoof frame height
register. The spoof frame ends when either JPEG bytes or uncompressed image data are
exhausted. Both kinds of data are always padded with dummy data to the programmed
spoof frame width.
60
Enable variable pixel clock rate: Setting this bit enables the adaptive pixel clock frequency
feature. The pixel clock is switched from PCLK1 to PCLK2 to PCLK3, depending on the
output FIFO fullness. When fullness reaches 50%, the pixel clock is switched from PCLK1 to
PCLK2. When the fullness reaches 75%, the clock is switched to PCLK3. As the FIFO fullness
drops below 50%, PIXCLK switches from PCLK3 to PCLK2; as it drops below 25%, it switches
back to PCLK1. At the start of a frame, it always starts with PCLK1.
70
Enable byte swap: Toggling this bit swaps the even and odd bytes in JPEG data stream. Byte
swapping supported only when enable spoof frame is set.
Table 7: IFP Registers, Page 2 (continued)
Reg # Bits Default Name