Datasheet

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MT9D111__4_REV5.fm - Rev. B 2/06 EN
53 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
IFP Registers, Page 2
Micron Confidential and Proprietary
5
0x05
5:0 0
JPEG Front End Configuration Register
00
Color component composition:
0
—4:2:2 format
1—4:2:0 format
10
JPEG monochrome mode. When this bit is set, the re-order buffer control sends only luma
data to the JPEG encoder.
6
0x06
0:0 0
JPEG Core Configuration Register - Extend JPEG Quantization Matrix
Presently, the JPEG encoder core supports two sets of quantization tables. (Each set contains a pair of
quantization tables - one for luma, one for chroma.) The quantization memory available allows an additional set
of quantization tables to be stored. By setting this bit, the encoder uses the third table pair. If reset, then
whichever set of tables 1 and 2 was programmed.
10
0x0A
0:0 1
JPEG Encoder Bypass
Set bit 0 of this register to have uncompressed frames from the SOC captured in the output FIFO and transferred
out as spoof frames (JPEG encoder is bypassed). Register 13, bit 0, should be set to “1” for spoof-mode output.
When the bit is cleared, JPEG-encoded frames are transferred out through the FIFO.
Table 7: IFP Registers, Page 2 (continued)
Reg # Bits Default Name