Datasheet

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MT9D111__4_REV5.fm - Rev. B 2/06 EN
52 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
IFP Registers, Page 2
Micron Confidential and Proprietary
IFP Registers, Page 2
Table 7: IFP Registers, Page 2
Reg # Bits Default Name
0
0x00
15:0 0
JPEG Control Register
00
Start/Enable Encoder: Enable JPEG encoding at the start of next frame.
10
Test SRAM: When set, allows host or microcontroller to take control of the output FIFO
buffer and the sixteen 800 x 16 RAMs in the re-order buffer for testing. Used in conjunction
with JPEG RAM test controls register to simultaneously write all 17 RAMs and individually
read each RAM.
[14:2]
Return zero when read.
15 0
Soft Reset.
2
0x02
15:0 0
JPEG Status Register 0
00
Transfer done status flag. When asserted, it indicates that the completion of transfer of the
JPEG-compressed image. This status flag remains set until cleared by the host or
microcontroller by writing “1” to bit [0]. Subsequently, the output FIFO overflow, the spoof
oversize error and the re-order buffer error status bits are reset. The output buffer clock
must be present to clear this bit.
10
Output FIFO overflow status flag. When asserted, it indicates that an overflow condition
was detected in the output FIFO during the frame transfer and that transfer was
terminated prematurely. This status flag remains set until cleared by the host or
microcontroller as it clears transfer done flag. Valid for JPEG compressed images only.
20
Spoof oversize error status flag. When asserted, it indicates that the spoof frame size is too
small for JPEG data stream. This status flag remains set until cleared by the host or
microcontroller as it clears transfer done flag. Valid for JPEG compressed images only.
30
Re-order buffer error status flag: When the re-order buffer detects an overflow or
underflow condition, this bit is set to “1.” This bit is cleared by writing a “1” to bit[0] of this
register.
5:4 0
Watermark of the output FIFO.
00
—less than 25% full
01—25% to less than 50% full
10—50% to less than 75% full
11
—75% full or more
Watermark is cleared when the host or microcontroller writes “1” to bit 4 of this register
(R258).
7:6 0
QTable_ID.
00
—Quantization table set 0
01
—Quantization table set 1
10—Quantization table set 2
11
—Reserved
15:8 0
JPEG data length bits 23:16. Highest byte of 24-bit JPEG data length.
3
0x03
15:0 0
JPEG Status Register 1 - JPEG Data Length Bits 15:0
This register combined with R2:2[15:8] gives the total number of data bytes successfully encoded
—a 24-bit JPEG
data length. If an output FIFO overflow occurs, this register holds the total number of data bytes already sent out
by the JPEG encoder (up to the point where the overflow occurs).
4
0x04
2:0 0
JPEG Status Register 2 - Output FIFO Fullness Status
Instantaneous FIFO fullness status code:
000
—FIFO is empty
001—0% < fullness < 25%
011
—25% <= fullness < 50%
010
—50% <= fullness < 75%
110—75% <= fullness <= 100%