Datasheet
Table Of Contents
- 1/3.2-Inch System-On-A-Chip (SOC) CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- General Description
- Feature Overview
- Typical Connection
- Ballout and Interface
- Architecture Overview
- Registers and Variables
- Registers
- Registers
- IFP Registers, Page 1
- IFP Registers, Page 2
- JPEG Indirect Registers
- Table 8: JPEG Indirect Registers (See Registers 30 and 31, Page 2)
- Firmware Driver Variables
- Table 9: Drivers IDs
- Table 10: Driver Variables-Monitor Driver (ID = 0)
- Table 11: Driver Variables-Sequencer Driver (ID = 1)
- Table 12: Driver Variables-Auto Exposure Driver (ID = 2)
- Table 13: Driver Variables-Auto White Balance (ID = 3)
- Table 14: Driver Variables-Flicker Detection Driver (ID = 4)
- Table 15: Driver Variables-Auto Focus Driver (ID = 5)
- Table 16: Driver Variables-Auto Focus Mechanics Driver (ID = 6)
- Table 17: Driver Variables-Mode/Context Driver (ID = 7)
- Table 18: Driver Variables-JPEG Driver (ID = 9)
- Table 19: Driver Variables-Histogram Driver (ID = 11)
- MCU Register List and Memory Map
- JPEG Indirect Registers
- Output Format and Timing
- Sensor Core
- Feature Description
- PLL Generated Master Clock
- PLL Setup
- Window Control
- Pixel Border
- Readout Modes
- Figure 20: 6 Pixels in Normal and Column Mirror Readout Modes
- Figure 21: 6 Rows in Normal and Row Mirror Readout Modes
- Table 30: Skip Values
- Figure 22: 8 Pixels in Normal and Column Skip 2x Readout Modes
- Figure 23: 16 Pixels in Normal and Column Skip 4x Readout Modes
- Figure 24: 32 Pixels in Normal and Column Skip 8x Readout Modes
- Figure 25: 64 Pixels in Normal and Column Skip 16x Readout Modes
- Table 31: Row Addressing
- Table 32: Column Addressing
- Frame Rate Control
- Context Switching
- Integration Time
- Flash STROBE
- Global Reset
- Analog Signal Path
- Analog Inputs AIN1-AIN3
- Firmware
- Firmware
- Start-Up and Usage
- General Purpose I/O
- Introduction
- GPIO Output Control Overview
- Waveform Programming
- Notification Signals
- Digital and Analog Inputs
- GPIO Software Drivers
- Auto Focus
- Figure 42: Search for Best Focus
- Figure 43: Scene with Two Potential Focus Targets at Different Distances from Camera
- Figure 44: Dependence of Luminance-Normalized Local Sharpness Scores on Lens Position
- Figure 45: Example of Position Weight Histogram Created by AF Driver
- Figure 46: Auto Focus Windows
- Figure 47: Computation of Sharpness Scores and Luminance Average for an AF Window
- Table 41: Examples of AF Filters that can be Programmed into the MT9D111
- Spectral Characteristics
- Electrical Specifications
- Packaging
- Appendix A: Two-Wire Serial Register Interface
- Protocol
- Sequence
- Bus Idle State
- Start Bit
- Stop Bit
- Slave Address
- Data Bit Transfer
- Acknowledge Bit
- No-Acknowledge Bit
- Page Register
- Sample Write and Read Sequences
- Figure 52: WRITE Timing to R0x09:0-Value 0x0284
- Figure 53: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 54: WRITE Timing to R0x09:0-Value 0x0284
- Figure 55: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 56: Two-Wire Serial Bus Timing Parameters
- Table 46: Two-wire Serial Bus Characteristics
- Revision History
PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__4_REV5.fm - Rev. B 2/06 EN
49 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
IFP Registers, Page 1
Micron Confidential and Proprietary
151
0x97
7:0 0
Output Format Configuration
00
In YUV output mode, swaps Cb and Cr channels. In RGB mode, swaps R and B. This bit
is subject to synchronous update.
10
Swaps chrominance byte with luminance byte in YUV output. In RGB mode, swaps odd
and even bytes. This bit is subject to synchronous update.
20
Reserved.
30
Monochrome output.
40
1 = use ITU-R BT.601 codes when bypassing FIFO.
(0xAB = frame start; 0x80 = line start; 0x9D = line end; 0xB6 = frame end.)
50
1 = output RGB (see R151[7:6])
0 = output YUV
7:6 0
RGB output format:
00 = 16-bit RGB565
01 = 15-bit RGB555
10 = 12-bit RGB444x
11 = 12-bit RGBx444
152
0x98
2:0 0
Output Format Test
00
1 = disable Cr channel (R in RGB mode).
10
1 = disable Y channel (G in RGB mode).
20
1 = disable Cb channel (B in RGB mode).
5:3 0
Test ramp output:
00
—off
01—by column
10—by row
11
—by frame
60
1 = enable 8+2 bypass.
70
1 = freeze update SOC registers affecting output size and format.
These include R151:1, R17-23:1.
153
0x99
11:0 R/O
Line Count
154
0x9A
15:0 R/O
Frame Count
164
0xA4
15:0 0x6440
Special Effects
2:0 0
Special effect selection bits:
0
—disabled
1
—monochrome
2
—sepia
3—negative
4
—solarization with unmodified UV
5
—solarization with -UV
5:3 0
Dither enable and amplitude. Valid values are 1..4, others disable.
61
1 = dither only in luma channel, 0 = dither in all color channels.
15:8 0
Solarization threshold for luma, divided by 2; 64..127.
165
0xA5
15:0 0xB023
Sepia Constants
7:0 35
Sepia constant for Cr.
15:8 176
Sepia constant for Cb.
Table 6: IFP Registers, Page 1 (continued)
Reg # Bits Default Name










