Datasheet

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MT9D111__4_REV5.fm - Rev. B 2/06 EN
43 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
IFP Registers, Page 1
Micron Confidential and Proprietary
IFP Registers, Page 1
Table 6: IFP Registers, Page 1
Reg # Bits Default Name
8
0x08
10:0 0x01F8
Color Pipeline Control
00
Toggles the assumption about Bayer CFA (vertical shift).
0
—row containing Blue comes first.
1—row with Red comes first.
10
Toggles the assumption about Bayer CFA (horizontal shift).
0
—Green comes first.
1—Red or Blue comes first.
20
1 = enable lens shading correction.
31
1 = enable on-the-fly defect correction.
41
1 = enable 2D aperture correction.
51
1 = enable color correction.
0 = bypass color correction (unity color matrix).
61
1 = invert output pixel clock (in all modes - JPEG, SOC, sensor).
71
1 = enable gamma correction.
81
1 = enable decimator.
90
1 = enable minblank. Allows len generation 2 lines earlier. Also adds 4 pixels to the line
size.
10 0
1 = enable 1D aperture correction.
9
0x09
4:0 0x000A
Factory Bypass
1:0 1
Data output bypass. Selects data going to D
OUT pads.
00 = 10-bit sensor.
01 = SOC.
10 = JPEG and output FIFO (no bypass). Reg16 and Reg17 (Page 2) have to be set to the
correct output frame size.
11 = Reserved.
20
Reserved.
4:3 1
GPIO output bypass.
00 = GPIO.
01 = FLASH is output on GPIO11.
10 = Reserved.
11 = Reserved.