Datasheet

PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__3_REV5.fm - Rev. A 2/06 EN
40 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Registers
Micron Confidential and Proprietary
R99—0x63 - Red Calibration Value (R/W)
Bits 8:0 Red
Calibration
Value
Analog calibration offset for red pixels, represented as a
two’s complement signed 8-bit value (if bit 8 is clear, the
offset is positive and the magnitude is given by bits 7:0. If
bit 8 is set, the offset is negative and the magnitude is given
by Not ([7:0]) + 1). If R0x60:0[0] = 0, this register is R/O and
returns the current value computed by the black level
calibration algorithm. If R0x60:0[0] = 1, this register is R/W
and can be used to manually set the calibration offset.
0 N Y
R100—0x64 - Green2 Calibration Value (R/W)
Bits 8:0 Green2
Calibration
Value
Analog calibration offset for green2 pixels, represented as a
two’s complement signed 8-bit value (if bit 8 is clear, the
offset is positive and the magnitude is given by bits 7:0. If
bit 8 is set, the offset is negative and the magnitude is given
by Not ([7:0]) + 1.) If R0x60:0[0] = 0, this register is R/O and
returns the current value computed by the black level
calibration algorithm. If R0x60:0[0] = 1, this register is R/W
and can be used to manually set the calibration offset.
Green2 pixels share rows with blue pixels.
0 N Y
R101—0x65 - Clock (R/W)
Bit 15 PLL Bypass 1—Bypass the PLL. Use CLKIN input signal as master clock.
0—Use clock produced by PLL as master clock.
1 N N
Bit 14 PLL Power-
down
1—Keep PLL in power-down to save power (default).
0—PLL powered-up.
1 N N
Bit 13 Power-down
PLL During
Standby
This register only has an effect when bit 14 = 0.
1
—Turn off PLL (power-down) during standby to save
power (default).
0—PLL powered-up during standby.
1 N N
Bit 2 clk_newrow Force clk_newrow to be on continuously.
0 N N
Bit 1 clk_newframe Force clk_newframe to be on continuously.
0 N N
Bit 0 clk_ship Force clk_ship to be on continuously.
0 N N
R102—0x66 - PLL Control 1 (R/W)
Bits 15:8 M M value for PLL must be 16 or higher.
28 N N
Bits 5:0 N N value for PLL.
9 N N
R103—0x67 - PLL Control 2 (R/W)
Bits 11:8 Reserved Do not change from default value.
Bits 6:0 P P value for PLL.
1 N N
R192—0xC0 - Global Reset Control (R/W)
Bit 15 Global Reset
Enable
Enter global reset. This bit is write - 1 only and is always
read 0.
0 N N
4
Bit 2 Global Reset
Flash Control
1—Flash is de-asserted at end of readout.
0
—Flash is de-asserted by R0xB6:0 (de-assert flash).
0 N N
Bit 1 Global Reset
Strobe Control
1—Strobe is de-asserted at end of readout.
0
—Strobe is de-asserted by R0xC4:0 (de-assert strobe).
0 N N
Table 5: Sensor Register Description (continued)
Bit
Field Description
Default
(Hex)
Sync’d to
Frame Start
Bad
Frame