Datasheet
Table Of Contents
- 1/3.2-Inch System-On-A-Chip (SOC) CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- General Description
- Feature Overview
- Typical Connection
- Ballout and Interface
- Architecture Overview
- Registers and Variables
- Registers
- Registers
- IFP Registers, Page 1
- IFP Registers, Page 2
- JPEG Indirect Registers
- Table 8: JPEG Indirect Registers (See Registers 30 and 31, Page 2)
- Firmware Driver Variables
- Table 9: Drivers IDs
- Table 10: Driver Variables-Monitor Driver (ID = 0)
- Table 11: Driver Variables-Sequencer Driver (ID = 1)
- Table 12: Driver Variables-Auto Exposure Driver (ID = 2)
- Table 13: Driver Variables-Auto White Balance (ID = 3)
- Table 14: Driver Variables-Flicker Detection Driver (ID = 4)
- Table 15: Driver Variables-Auto Focus Driver (ID = 5)
- Table 16: Driver Variables-Auto Focus Mechanics Driver (ID = 6)
- Table 17: Driver Variables-Mode/Context Driver (ID = 7)
- Table 18: Driver Variables-JPEG Driver (ID = 9)
- Table 19: Driver Variables-Histogram Driver (ID = 11)
- MCU Register List and Memory Map
- JPEG Indirect Registers
- Output Format and Timing
- Sensor Core
- Feature Description
- PLL Generated Master Clock
- PLL Setup
- Window Control
- Pixel Border
- Readout Modes
- Figure 20: 6 Pixels in Normal and Column Mirror Readout Modes
- Figure 21: 6 Rows in Normal and Row Mirror Readout Modes
- Table 30: Skip Values
- Figure 22: 8 Pixels in Normal and Column Skip 2x Readout Modes
- Figure 23: 16 Pixels in Normal and Column Skip 4x Readout Modes
- Figure 24: 32 Pixels in Normal and Column Skip 8x Readout Modes
- Figure 25: 64 Pixels in Normal and Column Skip 16x Readout Modes
- Table 31: Row Addressing
- Table 32: Column Addressing
- Frame Rate Control
- Context Switching
- Integration Time
- Flash STROBE
- Global Reset
- Analog Signal Path
- Analog Inputs AIN1-AIN3
- Firmware
- Firmware
- Start-Up and Usage
- General Purpose I/O
- Introduction
- GPIO Output Control Overview
- Waveform Programming
- Notification Signals
- Digital and Analog Inputs
- GPIO Software Drivers
- Auto Focus
- Figure 42: Search for Best Focus
- Figure 43: Scene with Two Potential Focus Targets at Different Distances from Camera
- Figure 44: Dependence of Luminance-Normalized Local Sharpness Scores on Lens Position
- Figure 45: Example of Position Weight Histogram Created by AF Driver
- Figure 46: Auto Focus Windows
- Figure 47: Computation of Sharpness Scores and Luminance Average for an AF Window
- Table 41: Examples of AF Filters that can be Programmed into the MT9D111
- Spectral Characteristics
- Electrical Specifications
- Packaging
- Appendix A: Two-Wire Serial Register Interface
- Protocol
- Sequence
- Bus Idle State
- Start Bit
- Stop Bit
- Slave Address
- Data Bit Transfer
- Acknowledge Bit
- No-Acknowledge Bit
- Page Register
- Sample Write and Read Sequences
- Figure 52: WRITE Timing to R0x09:0-Value 0x0284
- Figure 53: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 54: WRITE Timing to R0x09:0-Value 0x0284
- Figure 55: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 56: Two-Wire Serial Bus Timing Parameters
- Table 46: Two-wire Serial Bus Characteristics
- Revision History
PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__3_REV5.fm - Rev. A 2/06 EN
37 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Registers
Micron Confidential and Proprietary
Bits 6:0 Initial Gain Initial gain = bits 6:0*0.03125.
20 Y N
R44—0x2C - Blue Gain (R/W)
Bits 11:9 Digital Gain Total gain = (bit 9 + 1)*(bit 10 + 1)*(bit 11 + 1)*analog gain
(each bit gives 2x gain).
0 Y N
Bits 6:0 Initial Gain Initial gain = bits [6:0]*0.03125.
20 Y N
Bits 8:7 Analog Gain Analog gain = (bit 8 + 1)*(bit 7 + 1)*initial gain (each bit
gives 2x gain).
0 Y N
R45—0x2D - Red Gain (R/W)
Bits 11:9 Digital Gain Total gain = (bit 9 + 1)*(bit 10] + 1)*(bit 11 + 1)*analog gain
(each bit gives 2x gain).
0 Y N
Bits 8:7 Analog Gain Analog gain = (bit 8 + 1)*(bit 7 + 1)*initial gain (each bit
gives 2x gain).
0 Y N
Bits 6:0 Initial Gain Initial gain = bits 6:0*0.03125.
20 Y N
R46—0x2E - Green2 Gain (R/W)
Bits 11:9 Digital Gain Total gain = (bit 9 + 1)*(bit 10 + 1)*(bit 11 + 1)*analog gain
(each bit gives 2x gain).
0 Y N
Bits 8:7 Analog Gain Analog gain = (bit 8 + 1)*(bit 7 + 1)*initial gain (each bit
gives 2x gain).
0 Y N
Bits 6:0 Initial Gain Initial gain = bits 6:0*0.03125.
20 Y N
R47—0x2F - Global Gain (R/W)
Bits 11:0 Global Gain This register can be used to simultaneously set all 4 gains.
When read, it returns the value stored in R0x2B:0.
20 Y N
R48—0x30 - Row Noise (R/W)
Bit 15 Frame-wise
Digital
Correction
By default, the row noise is calculated and compensated for
individually for each color of each row. When this bit is set,
the row noise is calculated and applied for each color of
each of the first two 2 (two pairs of values) and the same
values are applied to each subsequent row, so that new
values are calculated and applied once per frame.
0 N N
Bits
14:12
Gain
Threshold
When the upper analog gain bits are equal to or larger
than this threshold, the dark column average is used in the
row noise correction algorithm. Otherwise, the subtracted
value is determined by bit 11. This check is independently
performed for each color, and is a means to turn off the
black level algorithm for lower gains.
0 N N
Bit 11 Use Black
Level Average
1—Use black level frame average from the dark rows in the
row noise correction algorithm for low gains. This frame
average was taken before the last adjustment of the offset
DAC for that frame, so it might be slightly off.
0
—Use mean of black level programmed threshold in the
row noise correction algorithm for low gains.
0 N Y
Bit 10 Enable
Correction
1—Enable row noise cancellation algorithm.
When this bit is set, the average value of the dark columns
read out is used as a correction for the whole row. The dark
average is subtracted from each pixel on the row, and then
a constant is added (bits 9:0).
0
—Normal operation.
1 N Y
Table 5: Sensor Register Description (continued)
Bit
Field Description
Default
(Hex)
Sync’d to
Frame Start
Bad
Frame










