Datasheet

PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__3_REV5.fm - Rev. A 2/06 EN
36 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Registers
Micron Confidential and Proprietary
Bit 10 End of Reset 1—In Xenon mode the flash is triggered after the resetting
of a frame.
0
—In Xenon mode the flash is triggered after the readout
of a frame.
1 N N
Bit 9 Every Frame 1—Flash should be enabled every frame.
0—Flash should be enabled for one frame only.
1 N N
Bit 8 LED Flash Enable LED flash. When set, FLASH output asserts prior to
the start of the resetting of a frame and remains asserted
until the end of the readout of the frame.
0 Y Y
1
Bits 7:0 Xenon Count Length of FLASH pulse when Xenon flash is enabled. The
value specifies the length in units of 1024*PIXCLK cycle
increments. When the Xenon count is set to its maximum
value (0xFF), the FLASH pulse is automatically truncated
prior to the readout of the first row, giving the longest
pulse possible.
8 N N
R36—0x24 - Extra Reset (R/W)
Bit 15 Extra Reset
Enable
0—Only programmed window (set by R0x01:0 through
R0x04:0) and black pixels are read.
1—Two additional rows are read and reset above and
below programmed window to prevent blooming to active
area.
1 N N
Bit 14 Next Row
Reset
When set, and the integration time is less than one frame
time, row (n + 1) is reset immediately prior to resetting row
(n). This is intended to prevent blooming across rows under
conditions of very high illumination.
0 N N
Bits 13:0 Reserved Do not change from default value.
R37—0x25 - LINE_VALID Control (R/W)
Bit 15 Xor
LINE_VALID
1—LINE_VALID = “continuous” LINE_VALID XOR
FRAME_VALID.
0
—Normal LINE_VALID (default, no XORing of LINE_VALID).
Ineffective if continuous LINE_VALID is set.
0 N N
Bit 14 Continuous
LINE_VALID
1—“Continuous” LINE_VALID (continue producing
LINE_VALID during vertical blanking).
0
—Normal LINE_VALID (default, no LINE_VALID during
vertical blanking).
0 N N
3
R38—0x26 - Bottom Dark Rows (R/W)
Bit 7 Show The bottom dark rows are visible in the image if the bit is
set.
0 N N
Bits 6:4 Start Address Defines the start address within the 8 bottom dark rows.
0 N N
Bit 3 Enable
Readout
Enable readout of the bottom dark rows.
0 N Y
Bits 2:0 Number of
Dark Rows
Defines the number of bottom dark rows to be used. (The
number of rows used is the specified value + 1.)
7 N Y
R43—0x2B - Green1 Gain (R/W)
Bits 11:9 Digital Gain Total gain = (bit 9 + 1)*(bit 10 + 1)*(bit 11 + 1)*analog gain
(each bit gives 2x gain).
0 Y N
Bits 8:7 Analog Gain Analog gain = (bit 8 + 1)*(bit 7 + 1)*initial gain (each bit
gives 2x gain).
0 Y N
Table 5: Sensor Register Description (continued)
Bit
Field Description
Default
(Hex)
Sync’d to
Frame Start
Bad
Frame