Datasheet

PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__3_REV5.fm - Rev. A 2/06 EN
35 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Registers
Micron Confidential and Proprietary
Bits 3:2 Row Skip—
Context A
When read mode context A is selected (R0xF2:0[3] = 0) and
Row skip is enabled (bit 4 = 1):
00
—Row Skip 2x
01
—Row Skip 4x
10—Row Skip 8x
11—Row Skip 16x
See “Column and Row Skip” on page 125 for more
information.
0 Y YM
R34—0x22 - Show Control (R/W)
Bit 10 Number of
Dark Columns
The MT9D111 has 40 dark columns.
1
—Read out 36 dark columns (4–39). Ignored during
binning, where all 40 dark columns are used.
0—Read out 20 dark columns (4–23).
0 N N
Bit 9 Show Dark
Columns
When set, the 20/36 (dependent on bit 10) dark columns are
output before the active pixels in a line. There is an idle
period of 2 pixels between readout of the dark columns
and readout of the active image. Therefore, when set,
LINE_VALID is asserted 22 pixel times earlier than normal,
and the horizontal blanking time is decreased by the same
amount.
0 N N
Bit 8 Read Dark
Columns
1—Enables the readout of dark columns for use in the row-
wise noise correction algorithm. The number of columns
used are 40 in binning mode, and otherwise determined by
bit 10.
0
—When disabled, an arbitrary number of dark columns
can be read out by including them in the active image.
Enabling the dark columns increases the minimum value for
horizontal blanking but does not affect the row time.
1 N Y
Bit 7 Show Dark
Rows
When set, the programmed dark rows is output before the
active window. FRAME_VALID is thus asserted earlier than
normal. This has no effect on integration time or frame
rate.
0 N N
Bits 6:4 Dark Start
Address
The start address for the dark rows within the 8 available
rows (an offset of 4 is added to compensate for the guard
pixels). Must be set so all dark rows read out falls in the
address space 0:7.
0 N N
Bit 3 Reserved Do not change from default value.
Bits 2:0 Num Dark
Rows
A value of N causes (n + 1) dark rows to be read out at the
start of each frame when dark row readout is enabled
(bit 3).
7 N Y
R35—0x23 - Flash Control (R/W)
Bit 15 FLASH Reflects the current state of FLASH output.
0
Bit 14 Triggered Indicates that FLASH output is asserted for the current
frame.
0
Bit 13 Xenon Flash Enable Xenon flash. When set, FLASH output asserts for the
programmed period (bits 7:0) during vertical blanking. This
is achieved by keeping the integration time equal to one
frame, and the pulse width less than the vertical blank time.
0 Y N
1
Bits
12:11
Frame Delay Delay of the flash pulse measured in frames.
0 N N
Table 5: Sensor Register Description (continued)
Bit
Field Description
Default
(Hex)
Sync’d to
Frame Start
Bad
Frame