Datasheet
Table Of Contents
- 1/3.2-Inch System-On-A-Chip (SOC) CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- General Description
- Feature Overview
- Typical Connection
- Ballout and Interface
- Architecture Overview
- Registers and Variables
- Registers
- Registers
- IFP Registers, Page 1
- IFP Registers, Page 2
- JPEG Indirect Registers
- Table 8: JPEG Indirect Registers (See Registers 30 and 31, Page 2)
- Firmware Driver Variables
- Table 9: Drivers IDs
- Table 10: Driver Variables-Monitor Driver (ID = 0)
- Table 11: Driver Variables-Sequencer Driver (ID = 1)
- Table 12: Driver Variables-Auto Exposure Driver (ID = 2)
- Table 13: Driver Variables-Auto White Balance (ID = 3)
- Table 14: Driver Variables-Flicker Detection Driver (ID = 4)
- Table 15: Driver Variables-Auto Focus Driver (ID = 5)
- Table 16: Driver Variables-Auto Focus Mechanics Driver (ID = 6)
- Table 17: Driver Variables-Mode/Context Driver (ID = 7)
- Table 18: Driver Variables-JPEG Driver (ID = 9)
- Table 19: Driver Variables-Histogram Driver (ID = 11)
- MCU Register List and Memory Map
- JPEG Indirect Registers
- Output Format and Timing
- Sensor Core
- Feature Description
- PLL Generated Master Clock
- PLL Setup
- Window Control
- Pixel Border
- Readout Modes
- Figure 20: 6 Pixels in Normal and Column Mirror Readout Modes
- Figure 21: 6 Rows in Normal and Row Mirror Readout Modes
- Table 30: Skip Values
- Figure 22: 8 Pixels in Normal and Column Skip 2x Readout Modes
- Figure 23: 16 Pixels in Normal and Column Skip 4x Readout Modes
- Figure 24: 32 Pixels in Normal and Column Skip 8x Readout Modes
- Figure 25: 64 Pixels in Normal and Column Skip 16x Readout Modes
- Table 31: Row Addressing
- Table 32: Column Addressing
- Frame Rate Control
- Context Switching
- Integration Time
- Flash STROBE
- Global Reset
- Analog Signal Path
- Analog Inputs AIN1-AIN3
- Firmware
- Firmware
- Start-Up and Usage
- General Purpose I/O
- Introduction
- GPIO Output Control Overview
- Waveform Programming
- Notification Signals
- Digital and Analog Inputs
- GPIO Software Drivers
- Auto Focus
- Figure 42: Search for Best Focus
- Figure 43: Scene with Two Potential Focus Targets at Different Distances from Camera
- Figure 44: Dependence of Luminance-Normalized Local Sharpness Scores on Lens Position
- Figure 45: Example of Position Weight Histogram Created by AF Driver
- Figure 46: Auto Focus Windows
- Figure 47: Computation of Sharpness Scores and Luminance Average for an AF Window
- Table 41: Examples of AF Filters that can be Programmed into the MT9D111
- Spectral Characteristics
- Electrical Specifications
- Packaging
- Appendix A: Two-Wire Serial Register Interface
- Protocol
- Sequence
- Bus Idle State
- Start Bit
- Stop Bit
- Slave Address
- Data Bit Transfer
- Acknowledge Bit
- No-Acknowledge Bit
- Page Register
- Sample Write and Read Sequences
- Figure 52: WRITE Timing to R0x09:0-Value 0x0284
- Figure 53: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 54: WRITE Timing to R0x09:0-Value 0x0284
- Figure 55: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 56: Two-Wire Serial Bus Timing Parameters
- Table 46: Two-wire Serial Bus Characteristics
- Revision History
PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__3_REV5.fm - Rev. A 2/06 EN
34 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Registers
Micron Confidential and Proprietary
Bit 4 Row Skip
Enable—
Context B
When read mode context B is selected (R0xF2:0[3] = 1):
1
—Enable row skip.
0—Normal readout.
0 Y YM
Bits 3:2 Row Skip—
Context B
When read mode context B is selected (R0xF2:0[3] = 1) and
Row skip is enabled (bit 4 = 1):
00
—Row Skip 2x
01—Row Skip 4x
10
—Row Skip 8x
11—Row Skip 16x
See “Column and Row Skip” on page 125 for more
information.
0 Y YM
Bit 1 Mirror
Columns
Read out columns from right to left (mirrored). When set,
column readout starts from column (column start + column
size) and continues down to (column start + 1). When clear,
readout starts at column start and continues to (column
start + column size - 1). This ensures that the starting color
is maintained.
0 Y YM
Bit 0 Mirror Rows Read out rows from bottom to top (upside down). When
set, row readout starts from row (row start + row size) and
continues down to (row start + 1). When clear, readout
starts at row start and continues to (row start + row size -1).
This ensures that the starting color is maintained.
0 Y YM
R33—0x21 - Read Mode—Context A (R/W)
Bit 15 Binning—
Context A
When read mode context A is selected (R0xF2:0[3] = 0):
0—Normal operation.
1
—Binning enabled. See “Binning” on page 127.
1 Y YM
Bit 10 Use 1 ADC—
Context A
When read mode context A is selected (R0xF2:0[3] = 0):
0—Use both ADCs to achieve maximum speed.
1—Use one ADC to reduce power. Maximum readout
frequency is now half of the master clock, and the pixel
clock is automatically adjusted as described for the pixel
clock speed register.
1 Y YM
Bit 7 Column Skip
Enable—
Context A
When read mode context A is selected (R0xF2:0[3] = 0):
1
—Enable column skip.
0
—Normal readout.
1 Y YM
Bits 6:5 Column Skip—
Context A
When read mode context A is selected (R0xF2:0[3] = 0) and
column skip is enabled (bit 7 = 1):
00
—Column Skip 2x
01—Column Skip 4x
10
—Column Skip 8x
11
—Column Skip 16x
See “Column and Row Skip” on page 125 for more
information.
0 Y YM
Bit 4 Row Skip
Enable—
Context A
When read mode context A is selected (R0xF2:0[3] = 0):
1
—Enable row skip.
0
—Normal readout.
1 Y YM
Table 5: Sensor Register Description (continued)
Bit
Field Description
Default
(Hex)
Sync’d to
Frame Start
Bad
Frame