Datasheet
Table Of Contents
- 1/3.2-Inch System-On-A-Chip (SOC) CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- General Description
- Feature Overview
- Typical Connection
- Ballout and Interface
- Architecture Overview
- Registers and Variables
- Registers
- Registers
- IFP Registers, Page 1
- IFP Registers, Page 2
- JPEG Indirect Registers
- Table 8: JPEG Indirect Registers (See Registers 30 and 31, Page 2)
- Firmware Driver Variables
- Table 9: Drivers IDs
- Table 10: Driver Variables-Monitor Driver (ID = 0)
- Table 11: Driver Variables-Sequencer Driver (ID = 1)
- Table 12: Driver Variables-Auto Exposure Driver (ID = 2)
- Table 13: Driver Variables-Auto White Balance (ID = 3)
- Table 14: Driver Variables-Flicker Detection Driver (ID = 4)
- Table 15: Driver Variables-Auto Focus Driver (ID = 5)
- Table 16: Driver Variables-Auto Focus Mechanics Driver (ID = 6)
- Table 17: Driver Variables-Mode/Context Driver (ID = 7)
- Table 18: Driver Variables-JPEG Driver (ID = 9)
- Table 19: Driver Variables-Histogram Driver (ID = 11)
- MCU Register List and Memory Map
- JPEG Indirect Registers
- Output Format and Timing
- Sensor Core
- Feature Description
- PLL Generated Master Clock
- PLL Setup
- Window Control
- Pixel Border
- Readout Modes
- Figure 20: 6 Pixels in Normal and Column Mirror Readout Modes
- Figure 21: 6 Rows in Normal and Row Mirror Readout Modes
- Table 30: Skip Values
- Figure 22: 8 Pixels in Normal and Column Skip 2x Readout Modes
- Figure 23: 16 Pixels in Normal and Column Skip 4x Readout Modes
- Figure 24: 32 Pixels in Normal and Column Skip 8x Readout Modes
- Figure 25: 64 Pixels in Normal and Column Skip 16x Readout Modes
- Table 31: Row Addressing
- Table 32: Column Addressing
- Frame Rate Control
- Context Switching
- Integration Time
- Flash STROBE
- Global Reset
- Analog Signal Path
- Analog Inputs AIN1-AIN3
- Firmware
- Firmware
- Start-Up and Usage
- General Purpose I/O
- Introduction
- GPIO Output Control Overview
- Waveform Programming
- Notification Signals
- Digital and Analog Inputs
- GPIO Software Drivers
- Auto Focus
- Figure 42: Search for Best Focus
- Figure 43: Scene with Two Potential Focus Targets at Different Distances from Camera
- Figure 44: Dependence of Luminance-Normalized Local Sharpness Scores on Lens Position
- Figure 45: Example of Position Weight Histogram Created by AF Driver
- Figure 46: Auto Focus Windows
- Figure 47: Computation of Sharpness Scores and Luminance Average for an AF Window
- Table 41: Examples of AF Filters that can be Programmed into the MT9D111
- Spectral Characteristics
- Electrical Specifications
- Packaging
- Appendix A: Two-Wire Serial Register Interface
- Protocol
- Sequence
- Bus Idle State
- Start Bit
- Stop Bit
- Slave Address
- Data Bit Transfer
- Acknowledge Bit
- No-Acknowledge Bit
- Page Register
- Sample Write and Read Sequences
- Figure 52: WRITE Timing to R0x09:0-Value 0x0284
- Figure 53: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 54: WRITE Timing to R0x09:0-Value 0x0284
- Figure 55: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 56: Two-Wire Serial Bus Timing Parameters
- Table 46: Two-wire Serial Bus Characteristics
- Revision History
PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__3_REV5.fm - Rev. A 2/06 EN
33 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Registers
Micron Confidential and Proprietary
Bit 13 Zoom Enable 0—Normal operation.
1
—Zoom is enabled, with zoom factor [zoom] defined in
bits 12:11.
In zoom mode, the pixel data rate is slowed by a factor of
[zoom]. This is achieved by outputting [zoom - 1] blank
rows between each output row. Setting this mode allows
the user to fill a window that is [zoom] times larger with
interpolated data.
The pixel clock speed is not affected by this operation, and
the output data for each pixel is valid for [zoom] pixel
clocks. Every row is followed by [zoom - 1] blank rows (with
their own LINE_VALID, but all data bits = 0) of equal time.
The combination of this register and an appropriate change
to the window sizing registers allows the user to zoom to a
region of interest without affecting the frame rate.
0 Y YM
Bits
12:11
Zoom When zoom is enabled by bit 13, this field determines the
zoom amount:
00
—Zoom 2x
01—Zoom 4x
10
—Zoom 8x
11—Zoom 16x
0 Y YM
Bit 10 Use 1 ADC—
Context B
When read mode context B is selected (bit 3, R0xF2:0 = 1):
0—Use both ADCs to achieve maximum speed.
1
—Use 1 ADC to reduce power. Maximum readout
frequency is now half the master clock frequency, and the
pixel clock is automatically adjusted as described for the
pixel clock speed register.
0 Y YM
Bit 9 Show Border This bit indicates whether to show the border enabled by
bit 8.
0—Border is enabled but not shown; vertical blanking is
increased by 8 rows and horizontal blanking is increased by
8 pixels.
1
—border is enabled and shown; FRAME_VALID time is
extended by 8 rows and LINE_VALID is extended by 8 pixels.
See “Pixel Border” on page 124.
0 N N
Bit 8 Over Sized 0—Normal UXGA size.
1
—Adds a 4-pixel border around the active image array
independent of readout mode (skip, zoom, mirror, etc.).
Setting this bit adds 8 to the number of rows and columns
in the frame.
0 Y YM
Bit 7 Column Skip
Enable—
Context B
When read mode context B is selected (R0xF2:0[3] = 1):
1
—Enable column skip.
0—Normal readout.
0 Y YM
Bits 6:5 Column Skip—
Context B
When read mode context B is selected (R0xF2:0[3] = 1) and
column skip is enabled (bit 7 = 1):
00
—Column Skip 2x
01—Column Skip 4x
10
—Column Skip 8x
11
—Column Skip 16x
See “Column and Row Skip” on page 125 for more
information.
0 Y YM
Table 5: Sensor Register Description (continued)
Bit
Field Description
Default
(Hex)
Sync’d to
Frame Start
Bad
Frame