Datasheet
Table Of Contents
- 1/3.2-Inch System-On-A-Chip (SOC) CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- General Description
- Feature Overview
- Typical Connection
- Ballout and Interface
- Architecture Overview
- Registers and Variables
- Registers
- Registers
- IFP Registers, Page 1
- IFP Registers, Page 2
- JPEG Indirect Registers
- Table 8: JPEG Indirect Registers (See Registers 30 and 31, Page 2)
- Firmware Driver Variables
- Table 9: Drivers IDs
- Table 10: Driver Variables-Monitor Driver (ID = 0)
- Table 11: Driver Variables-Sequencer Driver (ID = 1)
- Table 12: Driver Variables-Auto Exposure Driver (ID = 2)
- Table 13: Driver Variables-Auto White Balance (ID = 3)
- Table 14: Driver Variables-Flicker Detection Driver (ID = 4)
- Table 15: Driver Variables-Auto Focus Driver (ID = 5)
- Table 16: Driver Variables-Auto Focus Mechanics Driver (ID = 6)
- Table 17: Driver Variables-Mode/Context Driver (ID = 7)
- Table 18: Driver Variables-JPEG Driver (ID = 9)
- Table 19: Driver Variables-Histogram Driver (ID = 11)
- MCU Register List and Memory Map
- JPEG Indirect Registers
- Output Format and Timing
- Sensor Core
- Feature Description
- PLL Generated Master Clock
- PLL Setup
- Window Control
- Pixel Border
- Readout Modes
- Figure 20: 6 Pixels in Normal and Column Mirror Readout Modes
- Figure 21: 6 Rows in Normal and Row Mirror Readout Modes
- Table 30: Skip Values
- Figure 22: 8 Pixels in Normal and Column Skip 2x Readout Modes
- Figure 23: 16 Pixels in Normal and Column Skip 4x Readout Modes
- Figure 24: 32 Pixels in Normal and Column Skip 8x Readout Modes
- Figure 25: 64 Pixels in Normal and Column Skip 16x Readout Modes
- Table 31: Row Addressing
- Table 32: Column Addressing
- Frame Rate Control
- Context Switching
- Integration Time
- Flash STROBE
- Global Reset
- Analog Signal Path
- Analog Inputs AIN1-AIN3
- Firmware
- Firmware
- Start-Up and Usage
- General Purpose I/O
- Introduction
- GPIO Output Control Overview
- Waveform Programming
- Notification Signals
- Digital and Analog Inputs
- GPIO Software Drivers
- Auto Focus
- Figure 42: Search for Best Focus
- Figure 43: Scene with Two Potential Focus Targets at Different Distances from Camera
- Figure 44: Dependence of Luminance-Normalized Local Sharpness Scores on Lens Position
- Figure 45: Example of Position Weight Histogram Created by AF Driver
- Figure 46: Auto Focus Windows
- Figure 47: Computation of Sharpness Scores and Luminance Average for an AF Window
- Table 41: Examples of AF Filters that can be Programmed into the MT9D111
- Spectral Characteristics
- Electrical Specifications
- Packaging
- Appendix A: Two-Wire Serial Register Interface
- Protocol
- Sequence
- Bus Idle State
- Start Bit
- Stop Bit
- Slave Address
- Data Bit Transfer
- Acknowledge Bit
- No-Acknowledge Bit
- Page Register
- Sample Write and Read Sequences
- Figure 52: WRITE Timing to R0x09:0-Value 0x0284
- Figure 53: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 54: WRITE Timing to R0x09:0-Value 0x0284
- Figure 55: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 56: Two-Wire Serial Bus Timing Parameters
- Table 46: Two-wire Serial Bus Characteristics
- Revision History
PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__3_REV5.fm - Rev. A 2/06 EN
32 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Registers
Micron Confidential and Proprietary
Bit 2 Standby Setting this bit to 1 places the sensor in a low-power state.
Any attempt to access registers R[0xF7:0xFD]:0 in this state
results in a sensor hang-up. The sensor cannot recover from
it without a hard reset or power cycle.
0 N YM
Bit 1 Restart Setting this bit causes the sensor to truncate the current
frame and start resetting the first row. The delay before the
first valid frame is read out is equal to the integration time.
This bit is write - 1 but always reads back as 0.
0 N YM
Bit 0 Reset Setting this bit puts the sensor in reset; the frame being
generated is truncated and the pin interface goes to an idle
state. All internal registers (except for this bit) go to the
default power-up state. Clearing this bit resumes normal
operation.
0 N YM
R31—0x1F - FRAME_VALID Control (R/W)
Bit 15 Enable Early
FRAME_VALID
Fall
1—Enables the early disabling of FRAME_VALID as set in
bits 14:8. LINE_VALID is still generated for all active rows.
0
—Default. FRAME_VALID goes low 6 pixel clocks after last
LINE_VALID.
0 N N
Bits 14:8 Early
FRAME_VALID
Fall
When enabled, the FRAME_VALID falling edge occurs
within the programmed number of rows before the end of
the last LINE_VALID.
(1 + bits 14:8)*row time + constant
(constant = 3 in default mode)
The value of this field must not be larger than row width
R0x03:0.
0 N N
Bit 7 Enable Early
FRAME_VALID
Rise
1—Enables the early rise of FRAME_VALID as set in bits 6:0.
0
—Default. FRAME_VALID goes HIGH 6 pixel clocks before
first LINE_VALID.
0 N N
Bits 6:0 Early
FRAME_VALID
Rise
When enabled, the FRAME_VALID rising edge is set HIGH
the programmed number of rows before the first
LINE_VALID:
(1 + bits 6:0)*row time + horizontal blank + constant
(constant = 3 in default mode).
0 N N
R32—0x20 - Read Mode—Context B (R/W)
Bit 15 Binning—
Context B
When read mode context B is selected (R0xF2:0[3] = 1):
0—Normal operation.
1—Binning enabled. See “Binning” on page 127 and See
“Frame Rate Control” on page 128 for a full description.
0 Y YM
Table 5: Sensor Register Description (continued)
Bit
Field Description
Default
(Hex)
Sync’d to
Frame Start
Bad
Frame