Datasheet

PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__3_REV5.fm - Rev. A 2/06 EN
31 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Registers
Micron Confidential and Proprietary
R12—0x0C - Shutter Delay (R/W)
Bits 13:0 Shutter Delay The amount of time from the end of the sampling sequence
to the beginning of the pixel reset sequence. If the value in
this register exceeds the row time, the reset of the row does
not complete before the associated row is sampled, and the
sensor does not generate an image.
A programmed value of N reduces the integration time by
(N/2) pixel clock periods in 1 ADC mode and by N pixel clock
periods in 2 ADC mode.
0 Y N
R13—0x0D - Reset (R/W)
Bit 15 Synchronize
Changes
By default, update of many registers are synchronized to
frame start. Setting this bit inhibits this update; register
changes remain pending until this bit is returned to “0.”
When this bit is returned to “0,” all pending register
updates are made on the next frame start.
0 N N
Bit 10 Toggle SADDR By default, the sensor serial bus responds to addresses 0xBA
and 0xBB. When this bit is set, the sensor serial bus responds
to addresses 0x90 and 0x91. WRITEs to this bit are ignored
when STANDBY is asserted. See “Slave Address” on
page 181.
0 N N
Bit 9 Restart Bad
Frames
When set, a restart is forced to take place whenever a bad
frame is detected. This can shorten the delay when waiting
for a good frame because the delay, when masking out a
bad frame, is the integration time rather than the full
frame time.
0 N N
Bit 8 Show Bad
Frames
1—Output all frames (including bad frames).
0—Only output good frames (default).
A bad frame is defined as the first frame following a
change to: window size or position, horizontal blanking,
pixel clock speed, zoom, row or column skip, binning,
mirroring, or use of border.
0 N N
Bit 7:6 Inhibit
Standby /
Drive Pins
00 or 01—setting STANDBY high puts sensor into standby
state with high-impedance outputs
10
—setting STANDBY high only puts the outputs in High-Z
11
—causes STANDBY to be ignored
0 N N
Bit 5 Reset SOC When this bit is set to 1, SOC is put in reset state. It exits this
state when the bit is set back to 0.
Any attempt to access SOC registers (IFP page 1 and 2) in
the reset state results in a sensor hang-up. The sensor
cannot recover from it without a hard reset or power cycle.
0 N
Bit 4 Output
Disable
Setting this bit to 1 puts the pin interface in a High-Z. See
“Output Enable Control” on page 153. If the DOUT*,
PIXCLK, Frame_Valid, or Line_Valid is floating during
STANDBY, this bit should be set to “0” to turn off the input
buffer, reducing standby current (see technical note TN0934
“Standby Sequence”). This bit must work together with
bit 6 to take effect.
0
Bit 3 Reserved Keep at default value.
0
Table 5: Sensor Register Description (continued)
Bit
Field Description
Default
(Hex)
Sync’d to
Frame Start
Bad
Frame