Datasheet
Table Of Contents
- 1/3.2-Inch System-On-A-Chip (SOC) CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- General Description
- Feature Overview
- Typical Connection
- Ballout and Interface
- Architecture Overview
- Registers and Variables
- Registers
- Registers
- IFP Registers, Page 1
- IFP Registers, Page 2
- JPEG Indirect Registers
- Table 8: JPEG Indirect Registers (See Registers 30 and 31, Page 2)
- Firmware Driver Variables
- Table 9: Drivers IDs
- Table 10: Driver Variables-Monitor Driver (ID = 0)
- Table 11: Driver Variables-Sequencer Driver (ID = 1)
- Table 12: Driver Variables-Auto Exposure Driver (ID = 2)
- Table 13: Driver Variables-Auto White Balance (ID = 3)
- Table 14: Driver Variables-Flicker Detection Driver (ID = 4)
- Table 15: Driver Variables-Auto Focus Driver (ID = 5)
- Table 16: Driver Variables-Auto Focus Mechanics Driver (ID = 6)
- Table 17: Driver Variables-Mode/Context Driver (ID = 7)
- Table 18: Driver Variables-JPEG Driver (ID = 9)
- Table 19: Driver Variables-Histogram Driver (ID = 11)
- MCU Register List and Memory Map
- JPEG Indirect Registers
- Output Format and Timing
- Sensor Core
- Feature Description
- PLL Generated Master Clock
- PLL Setup
- Window Control
- Pixel Border
- Readout Modes
- Figure 20: 6 Pixels in Normal and Column Mirror Readout Modes
- Figure 21: 6 Rows in Normal and Row Mirror Readout Modes
- Table 30: Skip Values
- Figure 22: 8 Pixels in Normal and Column Skip 2x Readout Modes
- Figure 23: 16 Pixels in Normal and Column Skip 4x Readout Modes
- Figure 24: 32 Pixels in Normal and Column Skip 8x Readout Modes
- Figure 25: 64 Pixels in Normal and Column Skip 16x Readout Modes
- Table 31: Row Addressing
- Table 32: Column Addressing
- Frame Rate Control
- Context Switching
- Integration Time
- Flash STROBE
- Global Reset
- Analog Signal Path
- Analog Inputs AIN1-AIN3
- Firmware
- Firmware
- Start-Up and Usage
- General Purpose I/O
- Introduction
- GPIO Output Control Overview
- Waveform Programming
- Notification Signals
- Digital and Analog Inputs
- GPIO Software Drivers
- Auto Focus
- Figure 42: Search for Best Focus
- Figure 43: Scene with Two Potential Focus Targets at Different Distances from Camera
- Figure 44: Dependence of Luminance-Normalized Local Sharpness Scores on Lens Position
- Figure 45: Example of Position Weight Histogram Created by AF Driver
- Figure 46: Auto Focus Windows
- Figure 47: Computation of Sharpness Scores and Luminance Average for an AF Window
- Table 41: Examples of AF Filters that can be Programmed into the MT9D111
- Spectral Characteristics
- Electrical Specifications
- Packaging
- Appendix A: Two-Wire Serial Register Interface
- Protocol
- Sequence
- Bus Idle State
- Start Bit
- Stop Bit
- Slave Address
- Data Bit Transfer
- Acknowledge Bit
- No-Acknowledge Bit
- Page Register
- Sample Write and Read Sequences
- Figure 52: WRITE Timing to R0x09:0-Value 0x0284
- Figure 53: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 54: WRITE Timing to R0x09:0-Value 0x0284
- Figure 55: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 56: Two-Wire Serial Bus Timing Parameters
- Table 46: Two-wire Serial Bus Characteristics
- Revision History
PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__3_REV5.fm - Rev. A 2/06 EN
30 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Registers
Micron Confidential and Proprietary
R6—0x06 - Vertical Blanking—Context B (R/W)
Bits 14:0 Vertical
Blanking—
Context B
Number of blank rows in a frame when context B is selected
(R0xF2:0[1] = 1). The minimum supported value is
(4 + R0x22:0[2:0]). The actual vertical blanking time may be
controlled by the shutter width (R0x09:0). See “Raw Data
Timing” on page 119.
20 Y N
R7—0x07 - Horizontal Blanking—Context A (R/W)
Bits 13:0 Horizontal
Blanking—
Context A
Number of blank columns in a row when context A is
selected (R0xF2:0[0] = 0). The extra columns are added at
the beginning of a row. See “Frame Rate Control” on
page 128 for more information on supported register
values.
AE Y YM
R8—0x08 - Vertical Blanking—Context A (R/W)
Bits 14:0 Vertical
Blanking—
Context A
Number of blank rows in a frame when context A is chosen
(R0xF2:0[1] = 1). The minimum supported value is (4 +
R0x22:0[2:0]). The actual vertical blanking time may be
controlled by the shutter width (R0x9:0). See “Raw Data
Timing” on page 119.
10 Y N
R9—0x09 - Shutter Width (R/W)
Bits 15:0 Shutter Width Integration time in number of rows. The integration time is
also influenced by the shutter delay (R0x0C:0) and the
overhead time.
4D0 Y N
R10—0x0A - Row Speed (R/W)
Bits
15:14
Reserved Do not change from default value.
Bit 13 Reserved Do not change from default value.
Bit 8 Invert Pixel
Clock
Invert PIXCLK. When clear, FRAME_VALID, LINE_VALID, and
D
OUT are set up relative to the delayed rising edge of
PIXCLK. When set, FRAME_VALID, LINE_VALID, and DOUT
are set up relative to the delayed falling edge of PIXCLK.
0 N N
Bits 7:4 Delay Pixel
Clock
Number of half master clock cycle increments to delay the
rising edge of PIXCLK relative to transitions on
FRAME_VALID, LINE_VALID, and D
OUT.
1 N N
Bit 3 Reserved Do not change from default value..
Bits 2:0 Pixel Clock
Speed
A programmed value of N gives a pixel clock period of N
master clocks in 2 ADC mode and 2*N master clocks in 1
ADC mode. A value of “0” is treated like (and reads back as)
a value of “1.”
1 Y YM
R11—0x0B - Extra Delay (R/W)
Bits 13:0 Extra Delay Extra blanking inserted between frames. A programmed
value of N increases the vertical blanking time by N pixel
clock periods. Can be used to get a more exact frame rate. It
may affect the integration times of parts of the image
when the integration time is less than one frame.
0 Y N
2
Table 5: Sensor Register Description (continued)
Bit
Field Description
Default
(Hex)
Sync’d to
Frame Start
Bad
Frame