Datasheet

Table Of Contents
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MT9D111__3_REV5.fm - Rev. A 2/06 EN
29 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Registers
Micron Confidential and Proprietary
Registers
Notation used in the sensor register description table:
Sync’d to frame start
N = No. The register value is updated and used immediately.
Y = Yes. The register value is updated at next frame start as long as the synchronize changes bit
is 0. Frame start is defined as when the first dark row is read out. By default, this is 8 rows
before FRAME_VALID goes HIGH.
Bad frame
A bad frame is a frame where all rows do not have the same integration time, or offsets to the
pixel values changed during the frame.
N = No. Changing the register value does not produce a bad frame.
Y = Yes. Changing the register value might produce a bad frame.
YM = Yes, but the bad frame is masked out unless the “show bad frames” feature is
(R0x0D:0[8]) is enabled.
Table 5: Sensor Register Description
Bit
Field Description
Default
(Hex)
Sync’d to
Frame Start
Bad
Frame
R0—0x00 - Reserved (R/O)
Bits 15:0 Reserved Reserved.
1519
R1—0x01 - Row Start (R/W)
Bits 10:0 Row Start The first row to be read out, excluding any dark rows that
may be read. To window the image down, set this register
to the starting Y value. Setting a value less than 20 is not
recommended because the dark rows should be read using
R0x22:0.
1C Y YM
R2—0x02 - Column Start (R/W)
Bits 10:0 Column Start The first column to be read out, excluding dark columns
that may be read. To window the image down, set this
register to the starting X value. Setting a value below 52 is
not recommended because readout of dark columns should
be controlled by R0x22:0.
3C Y YM
R3—0x03 - Row Width (R/W)
Bits 10:0 Row Width Number of rows in the image to be read out, excluding any
dark rows or border rows that may be read. The minimum
supported value is 2.
4B0 Y YM
R4—0x04 - Column Width (R/W)
Bits 10:0 Column Width Number of columns in image to be read out, excluding any
dark columns or border columns that may be read. The
minimum supported value is 9 in 1 ADC mode and 17 in
2 ADC mode.
640 Y YM
R5—0x05 - Horizontal Blanking—Context B (R/W)
Bits 13:0 Horizontal
Blanking—
Context B
Number of blank columns in a row when context B is
selected (R0xF2:0[0] = 1). The extra columns are added at
the beginning of a row. See “Frame Rate Control” on
page 128 for more information on supported register
values.
15C Y YM