Datasheet

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MT9D111__2_REV5.fm - Rev. B 2/06 EN
19 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Architecture Overview
Micron Confidential and Proprietary
When a decision to adapt PIXCLK frequency is made, LINE_VALID, which qualifies the 8-
bit data output (D
OUT), is de-asserted until PIXCLK is safely switched to the new clock.
LINE_VALID is independent of the horizontal timing of the uncompressed imaged. Its
assertion is strictly based on compressed image data availability.
Should an output buffer overflow still occur with PIXCLK at the maximum frequency, the
output buffer and the small asynchronous FIFO is flushed immediately. This causes
LINE_VALID to be de-asserted. FRAME_VALID is also de-asserted.
In addition to the adaptive PIXCLK rate scheme, the MT9D111 also has storage for 3 sets
of quantization tables (6 tables). In the event of output buffer overflow during the com-
pression of the current frame, another set of the preloaded quantization tables can be
used for the encoding of the immediate next frame. Then, the MT9D111 starts com-
pressing the next frame starting with the nominal PIXCLK frequency.
Output Interface
Control (Two-Wire Serial Interface)
Camera control and JPEG configuration/control are accomplished via a two-wire serial
interface. The interface supports individual access to all camera function registers and
JPEG control registers. In particular, all tables located in the JPEG quantization and Huff-
man memories are accessible via the two-wire interface. To write to a particular register,
the external host processor must send the MT9D111 device address (selected by S
ADDR
or R0x0D:0[10]), the address of the register, and data to be written to it. See
“Appendix A: Two-Wire Serial Register Interface” on page 180 for a description of read
sequence and for details of the two-wire serial interface protocol.
Data
JPEG data is output in a BT656-like 8-bit parallel bus D
OUT0-DOUT7, with
FRAME_VALID, LINE_VALID, and PIXCLK. JPEG output data is valid when both
FRAME_VALID and LINE_VALID are asserted. When the JPEG data output for the frame
completes, or buffer overflow occurs, LINE_VALID and FRAME_VALID are de-asserted.
The output clock runs at frequencies selected by frequency divisors N1, N2, and N3 (reg-
isters R0x0E:2 and R0x0F:2), depending on output buffer fullness.