Datasheet

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MT9D111__7_REV5.fm - Rev. B 2/06 EN
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MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Appendix A: Two-Wire Serial Register Interface
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Bus Idle State
The bus is idle when both the data and clock lines are high. Control of the bus is initiated
with a start bit, and the bus is released with a stop bit. Only the master can generate start
and stop bits.
Start Bit
The start bit is defined as a HIGH-to-LOW data line transition while the clock line is
HIGH.
Stop Bit
The stop bit is defined as a LOW-to-HIGH data line transition while the clock line is
HIGH.
Slave Address
The 8-bit address of a two-wire serial interface device consists of seven bits of address
and one bit of direction. A “0” in the LSB (least significant bit) of the address indicates
write mode, and a “1” indicates read mode. The default slave addresses used by the sen-
sor core are 0xBA (write address) and 0xBB (read address). R0x0D:0[10] or the S
ADDR pin
can be used to select the alternate slave addresses 0x90 (write address) and 0x91 (read
address).
Writes to R0x0D:0[10] are inhibited when the standby pin is asserted (all other writes
proceed normally). This allows two sensors to co-exist as slaves on this interface, but
they must be addressed independently. Enable this capability as follows:
After RESET, both sensors use the default slave address. Reads or writes on the serial reg-
ister interface to the default slave address are decoded by both sensors simultaneously.
1. After RESET, assert the STANDBY signal to one sensor and negate the STANDBY signal
to the other sensor.
2. Perform a write to R0x0D:0 with bit 10 set. The sensor with STANDBY asserted ignores
the write to bit 10 and continues to decode at the default slave address.
The sensor with STANDBY negated has its R0x0D:0[10] set and responds to the alternate
slave address for all subsequent READ and WRITE operations, as shown in Table 45.
Data Bit Transfer
One data bit is transferred during each clock pulse. The serial interface clock pulse is
provided by the master. The data must be stable during the high period of the two-wire
serial interface clock—it can only change when the serial clock is low. Data is transferred
eight bits at a time, followed by an acknowledge bit.
Table 45: Slave Address Options
SADDR R0xD:0[10]
Slave Address
WRITE Read
0 0 0x090 0x091
01 0x0BA0x0BB
100x0BA0x0BB
1 1 0x090 0x091