Datasheet
Table Of Contents
- 1/3.2-Inch System-On-A-Chip (SOC) CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- General Description
- Feature Overview
- Typical Connection
- Ballout and Interface
- Architecture Overview
- Registers and Variables
- Registers
- Registers
- IFP Registers, Page 1
- IFP Registers, Page 2
- JPEG Indirect Registers
- Table 8: JPEG Indirect Registers (See Registers 30 and 31, Page 2)
- Firmware Driver Variables
- Table 9: Drivers IDs
- Table 10: Driver Variables-Monitor Driver (ID = 0)
- Table 11: Driver Variables-Sequencer Driver (ID = 1)
- Table 12: Driver Variables-Auto Exposure Driver (ID = 2)
- Table 13: Driver Variables-Auto White Balance (ID = 3)
- Table 14: Driver Variables-Flicker Detection Driver (ID = 4)
- Table 15: Driver Variables-Auto Focus Driver (ID = 5)
- Table 16: Driver Variables-Auto Focus Mechanics Driver (ID = 6)
- Table 17: Driver Variables-Mode/Context Driver (ID = 7)
- Table 18: Driver Variables-JPEG Driver (ID = 9)
- Table 19: Driver Variables-Histogram Driver (ID = 11)
- MCU Register List and Memory Map
- JPEG Indirect Registers
- Output Format and Timing
- Sensor Core
- Feature Description
- PLL Generated Master Clock
- PLL Setup
- Window Control
- Pixel Border
- Readout Modes
- Figure 20: 6 Pixels in Normal and Column Mirror Readout Modes
- Figure 21: 6 Rows in Normal and Row Mirror Readout Modes
- Table 30: Skip Values
- Figure 22: 8 Pixels in Normal and Column Skip 2x Readout Modes
- Figure 23: 16 Pixels in Normal and Column Skip 4x Readout Modes
- Figure 24: 32 Pixels in Normal and Column Skip 8x Readout Modes
- Figure 25: 64 Pixels in Normal and Column Skip 16x Readout Modes
- Table 31: Row Addressing
- Table 32: Column Addressing
- Frame Rate Control
- Context Switching
- Integration Time
- Flash STROBE
- Global Reset
- Analog Signal Path
- Analog Inputs AIN1-AIN3
- Firmware
- Firmware
- Start-Up and Usage
- General Purpose I/O
- Introduction
- GPIO Output Control Overview
- Waveform Programming
- Notification Signals
- Digital and Analog Inputs
- GPIO Software Drivers
- Auto Focus
- Figure 42: Search for Best Focus
- Figure 43: Scene with Two Potential Focus Targets at Different Distances from Camera
- Figure 44: Dependence of Luminance-Normalized Local Sharpness Scores on Lens Position
- Figure 45: Example of Position Weight Histogram Created by AF Driver
- Figure 46: Auto Focus Windows
- Figure 47: Computation of Sharpness Scores and Luminance Average for an AF Window
- Table 41: Examples of AF Filters that can be Programmed into the MT9D111
- Spectral Characteristics
- Electrical Specifications
- Packaging
- Appendix A: Two-Wire Serial Register Interface
- Protocol
- Sequence
- Bus Idle State
- Start Bit
- Stop Bit
- Slave Address
- Data Bit Transfer
- Acknowledge Bit
- No-Acknowledge Bit
- Page Register
- Sample Write and Read Sequences
- Figure 52: WRITE Timing to R0x09:0-Value 0x0284
- Figure 53: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 54: WRITE Timing to R0x09:0-Value 0x0284
- Figure 55: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 56: Two-Wire Serial Bus Timing Parameters
- Table 46: Two-wire Serial Bus Characteristics
- Revision History
PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__2_REV5.fm - Rev. B 2/06 EN
18 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Architecture Overview
Micron Confidential and Proprietary
Figure 5: JPEG Encoder Block Diagram
Output Buffer Overflow Prevention
The MT9D111 integrates SRAM for the storage of JPEG data. In order to prevent output
buffer overflow, the MT9D111 implements an adaptive pixel clock (PIXCLK) rate
scheme. When the adaptive pixel clock rate scheme is enabled, PIXCLK can run at clock
frequencies of (CLKIN freq/n1), (CLKIN freq/n2), (CLKIN freq/n3), where n1, n2, n3 are
register values programmed by the host via the two-wire serial interface. A clock divider
block from the master clock CLKIN generates the three clocks, PCLK1, PCLK2, and
PCLK3.
At the start of the frame encode, PIXCLK is sourced by PCLK1. The buffer fullness detec-
tion block of the SOC switches PIXCLK to PCLK2 and then to PCLK3, if necessary, based
on the watermark at the output buffer (i.e., percentage filled up). When the output buffer
watermark reaches 50 percent, PIXCLK switches to PCLK2. This increase in PIXCLK rate
unloads the output buffer at a higher rate. However, depending on the image complexity
and quantization table setting, the compressed image data may still be generated by the
JPEG encoder faster than PIXCLK can unload it. Should the output buffer watermark
equal 75 percent or higher, PIXCLK is switched to PCLK3. When the output buffer water-
mark drops back to 50 percent, PIXCLK is switched back to PCLK2. When the output
buffer watermark drops to 25 percent, PIXCLK is switched to PCLK1.
Re-order Line
Buffers (8Y + 8C)
Output Buffer
800 x 16
MUX
JPEG Encoder
Block
RegFile
2 x 16
IFP Register Bus
Data Unpacking
Data Packing
Spoof-frame
TIming Generator
Control Registers/Status
PIXCLK
D
OUT
0-D
OUT
7
LV
FV
Re-order Buffer
Controller
JPEG Input
Control
ITU-R BT. 601
Interface Control
Buffer Control
JPEG Encoder
Memories
Buffer Fullness
Detect
LD/UNLD
Control
Adaptive
PIXCLK
SOC_D
OUT (YCbCr or RGB)