Datasheet

PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__7_REV5.fm - Rev. B 2/06 EN
165 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
General Purpose I/O
Micron Confidential and Proprietary
In any case, the N
p
values occupy up to 8 registers (GPIO_WG_N0 through
GPIO_WG_N7). Writing an invalid N
p
= 0 to any of these registers is interpreted as setting
this particular N
p
to infinity. The T
ip
values are fully encoded in 42 registers named
GPIO_WG_T*, GPIO_WG_CLKDIV, and GPIO_WG_CLKDIV_SEL. This last two registers
contain, respectively, two 4-bit settings for two clock dividers and eight 1-bit switches
assigning one or the other divider to each of the GPIO[7:0] pads. Each clock divider
divides the GPIO clock frequency by 2
d+1
, where d is its 4-bit setting. The GPIO_WG_T*
registers contain natural numbers obtained by dividing the T
ip
values by master clock
period and by the appropriate power of 2. For example, suppose that the master clock
period is 12.5 ns. If one decides to use the registers (and counters) in the 16-bit mode
and sets the clock divider for the GPIO2 output to 2
2+1
= 8, one has to write 39 to
GPIO_WG_T03 and 16 to GPIO_WG_T02 to get T
02
= 1 ms. To obtain approximately the
same T
02
in the 8-bit mode with GPIO2 clock divider set to 2
8+1
= 512, one has to set the
GPIO_WG_T02 to 156 (since 1ms/12.5ns/512 = 156.25).
Bit values in registers GPIO_WG_FRAME_SYNC, GPIO_WG_STROBE_SYNC and
GPIO_WG_CHAIN determine the conditions that must be met for waveform generation
to begin on each of the GPIO[7:0] pads. It always has to be enabled first by clearing an
appropriate bit in GPIO_WG_SUSPEND register. Depending on selections made in the
GPIO_WG_*_SYNC and GPIO_WG_CHAIN registers, the enabling is the signal to either
start waveform generation immediately or on one of the following events: next falling
edge of FRAME_VALID, next raising edge of STROBE or end of waveform generation on
another pad. No more than one of these events should be chosen to trigger waveform
generation on each particular pad. If more than one event is selected, only selection
made in the highest priority register has an effect. The order of priority is, from highest
to lowest, GPIO_WG_CHAIN, GPIO_WG_FRAME_SYNC, GPIO_WG_STROBE_SYNC.
Waveform generation at any pad can be suspended and resumed at will using the
GPIO_WG_SUSPEND register. Suspending is like stopping the time on a particular pad.
If generation on other pads continues in the meantime, synchronization between the
suspended waveform and others are lost. Register GPIO_WG_RESET contain reset bits
for the GPIO[7:0] outputs. Setting any of them to 1 aborts ongoing waveform generation
at the corresponding pad and resets the counters used in it. The bit must be cleared
before the waveform generation can resume.
Notification Signals
The GPIO can send signals to the MCU to notify it about two types of events: the end of
waveform generation at a particular output pad (GPIO[7:0]) or a transition of interest
(LOW-to-HIGH or HIGH-to-LOW) on a particular input or output pad (GPIO[11:0]).
The GPIO uses two kinds of notification signals in parallel: on each event of interest, it
sends a wake-up signal to the MCU and it sets to 1 the appropriate bit in register
GPIO_NS_STATUS_L or GPIO_NS_STATUS_H. The bit remains set until acknowledged
by writing 1 to it. The wake-up signal has no effect unless the MCU is in sleep mode.
To enable notification signals from GPIO, some bits in register GPIO_NS_MASK_L and/
or register GPIO_NS_MASK_H must be set to 0. By writing to the corresponding bits in
registers GPIO_NS_TYPE, GPIO_NS_EDGE_L, and GPIO_N_EDGE_H, one can choose
events that triggers the signals.
Digital and Analog Inputs
All GPIO pads are configurable as high-impedance digital inputs. Setting or clearing bits
in the GPIO_DIR_* registers turns the corresponding pads into outputs or inputs,
respectively. The logical state of each input pad is mirrored by the state of the corre-
sponding bit in the GPIO_DATA_* registers, enabling the MCU or external host proces-
sor to receive digital feedback.