Datasheet

PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__7_REV5.fm - Rev. B 2/06 EN
150 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Start-Up and Usage
Micron Confidential and Proprietary
Figure 33: Power On/Off Sequence
Notes: 1. For a safe RESET to occur, CLKIN should be running during RESET with STANDBY LOW, as
shown in the sequence above.
2. After RESET# is HIGH, wait 24 CLKIN rising edges before the two-wire serial interface com-
munication is initiated.
3. After the power-up sequence, the preview state is reached when the firmware variable
seq.state (ID=1, Offset=4) is equal to 3. This transition time varies depending on the input
clock frequency and scene conditions.
4. In order to go into the firmware standby state, go to capture mode (also known as context
B), or execute the firmware REFRESH/REFRESH_MODE commands after the power-up
sequence (the preview state [seq.state=3] must be reached first).
Soft Reset Sequence
A soft reset to the camera can be activated by the following procedure:
1. Bypass the PLL, R0x65:0=0xA000, if it is currently used
2. Perform MCU reset by setting R0xC3:1=0x0501
3. Enable soft reset by setting R0x0D:0=0x0021. Bit 0 is used for the sensor core reset
while bit 5 refers to SOC reset.
4. Disable soft reset by setting R0x0D:0=0x0000
5. Wait 24 clock cycles before using the two-wire serial interface
Note: No access to MT9D111 registers—both page 1 and page 2—is possible during soft
reset.
Enable PLL
Since the input clock frequency is unknown, the part starts with PLL disabled. The
default MNP values are for 10 MHz, with 80 MHz as target. For other frequencies, calcu-
late and program appropriate MNP values. PLL programming and power-up sequence is
as follows:
1. Program PLL frequency settings, R0x66-67:0
2. Power up PLL, R0x65:0[14] = 0
3. Wait for PLL settling time >150µs
4. Turn off PLL bypass, R0x65:2[15] = 0
Allow one complete frame to effect the correct integration time after enabling PLL.
Note: Until PLL is enabled the two-wire serial interface may be limited in speed. After PLL is
enabled, the two-wire serial interface master can increase its communication speed.
VDD, VDDQ,
VAA, VAAPIX
RESET#
CLKIN
SCLK/SDATA (SHIP)
STANDBY
24-CLKIN
INACTIVE
INACTIVE
POWER
DOWN
POWER UP
RESET (>1μs)