Datasheet

PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__6_REV5.fm - Rev. B 2/06 EN
134 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Feature Description
Micron Confidential and Proprietary
Offset Voltage: VOFFSET
The offset voltage provides a constant offset to the ADC to fully utilize the ADC input
dynamic range. The offset voltages for green1, blue, red, and green2 pixels are manually
set by registers R0x61:0, R0x62:0, R0x63:0, and R0x64:0, respectively. The offset voltages
also can be automatically set by the black level calibration loop.
For a given color, the offset voltage, V
OFFSET, is determined by:
OFFSET_GAIN is determined by the 2-bit code from R0x5A:0[1:0], as shown in Table 35.
These step sizes are not exact; increasing the stage0 ADC gain from 2 to 4 decreases the
step size significance; decreasing the ADC V
REFD increases the step size significance.
Recommended Gain Settings
The analog gain circuitry in the sensor core provides signal gains from 1 through 15.875.
Analog Inputs AIN1–AIN3
Since ADC resources in the sensor core are not used to digitize pixel array output
100 percent of the time, they can be intermittently used to sample external analog sig-
nals coming from a variety of sources—e.g., a flash charging circuit or an auto focus lens
actuator. If R0xE3:0[15] = 1, the chip samples AIN1–AIN3 once per every pixel array row
(after reading out the row). Digital data produced by this sampling are available to the
user in two ways:
• They can be read from registers R0xE0:0 through R0xE2:0.
• If R0xE3:0[14] = 1, the data are additionally inserted into image data stream each time
LINE_VALID goes LOW.
The nominal range of AIN are 0V + V
OFFSET to VREFD + VOFFSET. VREFD is the ADC
reference voltage (nominally 1V), but can be programmed. (See “Analog Signal Path” on
page 132.) V
OFFSET is the offset in the ADC and is typically ±10mV to 20mV. If required,
the offset can be measured by converting a calibrated reference voltage, which can be
VOFFSET = 0.50V*offset_gain*offset_sign*offset_code[7:0]/255
(13)
where: “offset_sign” is determined by bit 8 as:
if bit 8 = 0, offset_sign = +1
(14)
if bit 8 = 1, offset_sign = -1
(15)
“offset_code” is the decimal value of bit<7:0>
Table 35: Offset Gain
R0x5A:0[1:0] OFFSET_GAIN
00
OFFSET_GAIN = 0 (no calibration voltage is applied)
01
OFFSET_GAIN = 0.25 (1 calibration LSB is equal to 0.5 ADC LSB when V
REFD = 1V)
10
OFFSET_GAIN = 0.50 (1 calibration LSB is equal to 1 ADC LSB when V
REFD = 1V)
11
OFFSET_GAIN = 1 (1 calibration LSB is equal to 2 ADC LSB when V
REFD = 1V)
Table 36: Recommended Gain Settings
Desired Gain Recommended Gain Register Setting
1–1.969 0x020–0x03F
2–7.938 0x0A0–0x0FF
8–15.875 0x1C0–0x1FF