Datasheet
Table Of Contents
- 1/3.2-Inch System-On-A-Chip (SOC) CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- General Description
- Feature Overview
- Typical Connection
- Ballout and Interface
- Architecture Overview
- Registers and Variables
- Registers
- Registers
- IFP Registers, Page 1
- IFP Registers, Page 2
- JPEG Indirect Registers
- Table 8: JPEG Indirect Registers (See Registers 30 and 31, Page 2)
- Firmware Driver Variables
- Table 9: Drivers IDs
- Table 10: Driver Variables-Monitor Driver (ID = 0)
- Table 11: Driver Variables-Sequencer Driver (ID = 1)
- Table 12: Driver Variables-Auto Exposure Driver (ID = 2)
- Table 13: Driver Variables-Auto White Balance (ID = 3)
- Table 14: Driver Variables-Flicker Detection Driver (ID = 4)
- Table 15: Driver Variables-Auto Focus Driver (ID = 5)
- Table 16: Driver Variables-Auto Focus Mechanics Driver (ID = 6)
- Table 17: Driver Variables-Mode/Context Driver (ID = 7)
- Table 18: Driver Variables-JPEG Driver (ID = 9)
- Table 19: Driver Variables-Histogram Driver (ID = 11)
- MCU Register List and Memory Map
- JPEG Indirect Registers
- Output Format and Timing
- Sensor Core
- Feature Description
- PLL Generated Master Clock
- PLL Setup
- Window Control
- Pixel Border
- Readout Modes
- Figure 20: 6 Pixels in Normal and Column Mirror Readout Modes
- Figure 21: 6 Rows in Normal and Row Mirror Readout Modes
- Table 30: Skip Values
- Figure 22: 8 Pixels in Normal and Column Skip 2x Readout Modes
- Figure 23: 16 Pixels in Normal and Column Skip 4x Readout Modes
- Figure 24: 32 Pixels in Normal and Column Skip 8x Readout Modes
- Figure 25: 64 Pixels in Normal and Column Skip 16x Readout Modes
- Table 31: Row Addressing
- Table 32: Column Addressing
- Frame Rate Control
- Context Switching
- Integration Time
- Flash STROBE
- Global Reset
- Analog Signal Path
- Analog Inputs AIN1-AIN3
- Firmware
- Firmware
- Start-Up and Usage
- General Purpose I/O
- Introduction
- GPIO Output Control Overview
- Waveform Programming
- Notification Signals
- Digital and Analog Inputs
- GPIO Software Drivers
- Auto Focus
- Figure 42: Search for Best Focus
- Figure 43: Scene with Two Potential Focus Targets at Different Distances from Camera
- Figure 44: Dependence of Luminance-Normalized Local Sharpness Scores on Lens Position
- Figure 45: Example of Position Weight Histogram Created by AF Driver
- Figure 46: Auto Focus Windows
- Figure 47: Computation of Sharpness Scores and Luminance Average for an AF Window
- Table 41: Examples of AF Filters that can be Programmed into the MT9D111
- Spectral Characteristics
- Electrical Specifications
- Packaging
- Appendix A: Two-Wire Serial Register Interface
- Protocol
- Sequence
- Bus Idle State
- Start Bit
- Stop Bit
- Slave Address
- Data Bit Transfer
- Acknowledge Bit
- No-Acknowledge Bit
- Page Register
- Sample Write and Read Sequences
- Figure 52: WRITE Timing to R0x09:0-Value 0x0284
- Figure 53: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 54: WRITE Timing to R0x09:0-Value 0x0284
- Figure 55: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 56: Two-Wire Serial Bus Timing Parameters
- Table 46: Two-wire Serial Bus Characteristics
- Revision History
PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__6_REV5.fm - Rev. B 2/06 EN
133 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Feature Description
Micron Confidential and Proprietary
Figure 30: Analog Readout Channel
Stage-by-Stage Transfer Functions
Transfer functions proceed stage-by-stage, as follows:
Where
G1, G2, and G3 are the gain settings, V
OFFSET
is the offset (calibration) voltage, and
V
REFD
is the reference voltage of the ADC. The gain setting G3 is applied to the signal but
is not applied to V
OFFSET
. The parameters V
REFD
, G1, G2, G3, and V
OFFSET
are described
next.
VREFD
The VREFD parameters are as follows:
Gain Settings: G1, G2, G3
The gains for green1, blue, red, and green2 pixels are set by registers R0x2B:0, R0x2C:0,
R0x2D:0, and R0x2E:0, respectively. Gain can also be globally set by R0x2F:0. The analog
gain is set by bits 8:0 of the corresponding register as follows:
Digital gain is set by bits 11:9 of the same registers.
Let VPIX be the input of the signal path: VPIX = pixel output voltage = signal path
input voltage,
The output voltage of ASC 1st stage is: V1 = -1*G1*V
PIX
(1)
The output voltage of ASC 2nd stage is: V2 = -1*G2*V1
(2)
The output voltage of ADC Sample-and-
Hold stage is:
V3 = 2*G3*V2 - V
REFD + VOFFSET
(3)
and the ADC output code is: ADC output code = 511*(1 + (V3 / Vr
EFD))
(4)
From (1) to (4), the ADC output code can
also be written as:
ADC code = (1022/VREFD)*[G1*G2*G3*VPIX +
(Voffset/(2*G3))]
(5)
The ADC reference voltage VREFD Is: VREFD = VREF_HI - VREF_LO
(6)
where V
REF_HI = 55.5mV*(R0x41:0[7:4] + 23)
(7)
using default register values: V
REF_HI = 55.5mV*(13 + 23) = 1.998V
and VREF_LO = 55.5mV*(R0x41:0[3:0] +11)
(8)
using default register values: V
REF_LO = 55.5mV*(7 +11) = 0.999V
so V
REFD = 55.5mV*(R0x41:0[7:4] - R0x41:0[3:0] + 12)
(9)
using default register values VREFD = 1.998 - 0.999 = 0.999V
G1 = bit 7 + 1
(10)
G2 = bit 6:0 / 32
(11)
G3 = bit 8 + 1
(12)
ASC1 ASC2 ADCSH 10-bit
(G1) (G2) (G3) ADC
V1 V2 V3
Vpix
ADC_code
10
V
OFFSET VREFD
+