Datasheet
Table Of Contents
- 1/3.2-Inch System-On-A-Chip (SOC) CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- General Description
- Feature Overview
- Typical Connection
- Ballout and Interface
- Architecture Overview
- Registers and Variables
- Registers
- Registers
- IFP Registers, Page 1
- IFP Registers, Page 2
- JPEG Indirect Registers
- Table 8: JPEG Indirect Registers (See Registers 30 and 31, Page 2)
- Firmware Driver Variables
- Table 9: Drivers IDs
- Table 10: Driver Variables-Monitor Driver (ID = 0)
- Table 11: Driver Variables-Sequencer Driver (ID = 1)
- Table 12: Driver Variables-Auto Exposure Driver (ID = 2)
- Table 13: Driver Variables-Auto White Balance (ID = 3)
- Table 14: Driver Variables-Flicker Detection Driver (ID = 4)
- Table 15: Driver Variables-Auto Focus Driver (ID = 5)
- Table 16: Driver Variables-Auto Focus Mechanics Driver (ID = 6)
- Table 17: Driver Variables-Mode/Context Driver (ID = 7)
- Table 18: Driver Variables-JPEG Driver (ID = 9)
- Table 19: Driver Variables-Histogram Driver (ID = 11)
- MCU Register List and Memory Map
- JPEG Indirect Registers
- Output Format and Timing
- Sensor Core
- Feature Description
- PLL Generated Master Clock
- PLL Setup
- Window Control
- Pixel Border
- Readout Modes
- Figure 20: 6 Pixels in Normal and Column Mirror Readout Modes
- Figure 21: 6 Rows in Normal and Row Mirror Readout Modes
- Table 30: Skip Values
- Figure 22: 8 Pixels in Normal and Column Skip 2x Readout Modes
- Figure 23: 16 Pixels in Normal and Column Skip 4x Readout Modes
- Figure 24: 32 Pixels in Normal and Column Skip 8x Readout Modes
- Figure 25: 64 Pixels in Normal and Column Skip 16x Readout Modes
- Table 31: Row Addressing
- Table 32: Column Addressing
- Frame Rate Control
- Context Switching
- Integration Time
- Flash STROBE
- Global Reset
- Analog Signal Path
- Analog Inputs AIN1-AIN3
- Firmware
- Firmware
- Start-Up and Usage
- General Purpose I/O
- Introduction
- GPIO Output Control Overview
- Waveform Programming
- Notification Signals
- Digital and Analog Inputs
- GPIO Software Drivers
- Auto Focus
- Figure 42: Search for Best Focus
- Figure 43: Scene with Two Potential Focus Targets at Different Distances from Camera
- Figure 44: Dependence of Luminance-Normalized Local Sharpness Scores on Lens Position
- Figure 45: Example of Position Weight Histogram Created by AF Driver
- Figure 46: Auto Focus Windows
- Figure 47: Computation of Sharpness Scores and Luminance Average for an AF Window
- Table 41: Examples of AF Filters that can be Programmed into the MT9D111
- Spectral Characteristics
- Electrical Specifications
- Packaging
- Appendix A: Two-Wire Serial Register Interface
- Protocol
- Sequence
- Bus Idle State
- Start Bit
- Stop Bit
- Slave Address
- Data Bit Transfer
- Acknowledge Bit
- No-Acknowledge Bit
- Page Register
- Sample Write and Read Sequences
- Figure 52: WRITE Timing to R0x09:0-Value 0x0284
- Figure 53: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 54: WRITE Timing to R0x09:0-Value 0x0284
- Figure 55: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 56: Two-Wire Serial Bus Timing Parameters
- Table 46: Two-wire Serial Bus Characteristics
- Revision History
PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__6_REV5.fm - Rev. B 2/06 EN
132 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Feature Description
Micron Confidential and Proprietary
Global Reset
The sensor core provides a global reset mode in which the pixel integration time is con-
trolled by an external mechanical shutter. The sensor can then operate on a lower clock
frequency, reducing the bandwidth on the interface between the sensor and the host
processor without losing image quality.
The basic operation is as follows:
1. The sensor operates in either preview or full-frame mode (electronic rolling shutter
[ERS]).
2. A rising edge on the signal GRST_CTR or a WRITE to an internal register starts the glo-
bal reset sequence.
3. The sensor now enters the snapshot mode and after a certain time, all the lines in the
sensor array are reset and kept in a reset state until the integration starts.
The start of the integration (exposure) period, the assertion of STROBE, the start of the
readout, and the de-assertion of STROBE can be controlled by internal registers (T1, T2,
T3, and T4, as shown in Figure 29).
The sensor core provides an output signal, STROBE, that can be used to control the
mechanical shutter. This signal can be programmed to occur in a specified window
around the actual start of integration. During global reset, FLASH is programmed in a
different way than during normal ERS operation. Normally, the FLASH behavior is pro-
grammed using R0x23:0. In global reset mode, FLASH is programmed in the same way as
STROBE, showed in Figure 29, using registers R0xC5:0 and R0xC6:0.
R0xC0:0[0] controls the mechanism for starting the readout after a GLOBAL RESET oper-
ation. If this bit is HIGH, the integration time is directly controlled by GRST_CTR. Very
long integration times can be achieved this way.
Figure 29: GLOBAL RESET Operation
Analog Signal Path
The sensor core features two identical analog readout channels. A block diagram for one
channel is shown in Figure 30. The readout channel consists of two gain stages (ASC1
and ASC2), a sample-and-hold (ADCSH) stage with black level calibration capability
(V
OFFSET), and a 10-bit ADC.
Global Reset
Complete
Integration Starts Readout Can Start
ERS Mode
Snapshot Mode
E
R
S
m
ERS Mode
Reset Pixel Array Integration until shutter close Readout FrameWait
GRST_CTR
STROBE
T1
T2
T3
T4