Datasheet
Table Of Contents
- 1/3.2-Inch System-On-A-Chip (SOC) CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- General Description
- Feature Overview
- Typical Connection
- Ballout and Interface
- Architecture Overview
- Registers and Variables
- Registers
- Registers
- IFP Registers, Page 1
- IFP Registers, Page 2
- JPEG Indirect Registers
- Table 8: JPEG Indirect Registers (See Registers 30 and 31, Page 2)
- Firmware Driver Variables
- Table 9: Drivers IDs
- Table 10: Driver Variables-Monitor Driver (ID = 0)
- Table 11: Driver Variables-Sequencer Driver (ID = 1)
- Table 12: Driver Variables-Auto Exposure Driver (ID = 2)
- Table 13: Driver Variables-Auto White Balance (ID = 3)
- Table 14: Driver Variables-Flicker Detection Driver (ID = 4)
- Table 15: Driver Variables-Auto Focus Driver (ID = 5)
- Table 16: Driver Variables-Auto Focus Mechanics Driver (ID = 6)
- Table 17: Driver Variables-Mode/Context Driver (ID = 7)
- Table 18: Driver Variables-JPEG Driver (ID = 9)
- Table 19: Driver Variables-Histogram Driver (ID = 11)
- MCU Register List and Memory Map
- JPEG Indirect Registers
- Output Format and Timing
- Sensor Core
- Feature Description
- PLL Generated Master Clock
- PLL Setup
- Window Control
- Pixel Border
- Readout Modes
- Figure 20: 6 Pixels in Normal and Column Mirror Readout Modes
- Figure 21: 6 Rows in Normal and Row Mirror Readout Modes
- Table 30: Skip Values
- Figure 22: 8 Pixels in Normal and Column Skip 2x Readout Modes
- Figure 23: 16 Pixels in Normal and Column Skip 4x Readout Modes
- Figure 24: 32 Pixels in Normal and Column Skip 8x Readout Modes
- Figure 25: 64 Pixels in Normal and Column Skip 16x Readout Modes
- Table 31: Row Addressing
- Table 32: Column Addressing
- Frame Rate Control
- Context Switching
- Integration Time
- Flash STROBE
- Global Reset
- Analog Signal Path
- Analog Inputs AIN1-AIN3
- Firmware
- Firmware
- Start-Up and Usage
- General Purpose I/O
- Introduction
- GPIO Output Control Overview
- Waveform Programming
- Notification Signals
- Digital and Analog Inputs
- GPIO Software Drivers
- Auto Focus
- Figure 42: Search for Best Focus
- Figure 43: Scene with Two Potential Focus Targets at Different Distances from Camera
- Figure 44: Dependence of Luminance-Normalized Local Sharpness Scores on Lens Position
- Figure 45: Example of Position Weight Histogram Created by AF Driver
- Figure 46: Auto Focus Windows
- Figure 47: Computation of Sharpness Scores and Luminance Average for an AF Window
- Table 41: Examples of AF Filters that can be Programmed into the MT9D111
- Spectral Characteristics
- Electrical Specifications
- Packaging
- Appendix A: Two-Wire Serial Register Interface
- Protocol
- Sequence
- Bus Idle State
- Start Bit
- Stop Bit
- Slave Address
- Data Bit Transfer
- Acknowledge Bit
- No-Acknowledge Bit
- Page Register
- Sample Write and Read Sequences
- Figure 52: WRITE Timing to R0x09:0-Value 0x0284
- Figure 53: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 54: WRITE Timing to R0x09:0-Value 0x0284
- Figure 55: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 56: Two-Wire Serial Bus Timing Parameters
- Table 46: Two-wire Serial Bus Characteristics
- Revision History
PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__6_REV5.fm - Rev. B 2/06 EN
128 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Feature Description
Micron Confidential and Proprietary
• Start address must be divisible by four (row and column).
• Window size must be divisible by four in both directions, after dividing by zoom factor
and skip factor (because they both reduce the effective window size from the sensor’s
point of view).
Example: Default row size = 1,200. 8x zoom means the actual window on the sensor is
divided by 8, so 8x zoom and binning is not allowed with default window size, because
1,200 / 8 = 150, which is not divisible by 4.
• Binning can be seen as an extra level of skip. The combination binning/16x skip is
therefore not legal.
Frame Rate Control
For a given window size, the blanking registers (R0x05:0 - R0x08:0) along with the row
speed register (R0x0A:0) can be used to set a particular frame rate.
The frame timing equations (Table 27 and Table 28 on page 120) can be rearranged to
express the horizontal blanking or vertical blanking values as a function of the frame
rate:
The HBLANK_REG value allows the frame rate to be adjusted with a minimum resolu-
tion of one PIXCLK_PERIOD multiplied by the total number of rows (displayed plus
blanking). When finer resolution is required, R0x0B:0 (extra delay) can be used. R0x0B:0
allows the frame time to be changed in increments of pixel clocks.
Minimum Horizontal Blanking
The minimum horizontal blanking value is constrained by the time used for sampling a
row of pixels and the overhead in the row readout. This is expressed in Table 33.
Minimum Row Time Requirement
The total row time must be sufficient to allow all row operations (readout and shutter
operations). The row time is the sum of column width (halved during binning divided by
column skip factor) and horizontal blanking, and can therefore be adjusted by program-
ming these.
Table 34 shows minimum row time as a function of mode of operation.
This is a particularly strict requirement during binning because twice as many row oper-
ations are required per row and the column width is halved.
HBLANK_REG =
master clock freq / (frame rate*
((R0x03:0/S + BORDER) + VBLANK_REG)*PIXCLK_PERIOD) - (R0x04:0/S +
BORDER)
VBLANK_REG =
master clock freq / (frame rate*
((R0x04:0/S + BORDER) + HBLANK_REG)*PIXCLK_PERIOD) - (R0x03:0/S +
BORDER)
Table 33: Minimum Horizontal Blanking Parameters
Parameter
Default / 2 ADC Mode,
No Binning
1 ADC Mode,
No Binning 2 ADC Mode, Binning 1 ADC Mode, Binning
HBLANK(MIN) 286 mclks 324 mclks
= 162 pixclks
470 mclks 508 mclks
= 254 pixclks