Datasheet

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MT9D111__6_REV5.fm - Rev. B 2/06 EN
123 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Feature Description
Micron Confidential and Proprietary
Feature Description
PLL Generated Master Clock
The PLL embedded in the sensor core can generate a master clock signal whose fre-
quency is up to 80 MHz (input clock from 6 MHz through 64 MHz). Registers R0x66:0
and R0x67:0 control the frequency of the PLL-generated clock. It is possible to bypass the
PLL and use CLKIN as master clock. In order to do so, one must set R0x65:0[15] to 1. If
power consumption is a concern, R0x65:0[14] should be also set to 1 a short time later, to
put the bypassed PLL in power down mode. To enable the PLL again, the two bits must
be set to 0 in the reverse order. By default, the PLL is bypassed and powered down.
PLL Setup
The PLL output frequency is determined by three constants (M, N, and P) and the input
clock frequency. These three values are set in:
R102:0// [15:8] for M; [5:0] for N
R103:0// [6:0] for P
Their relations can be shown by the following equation:
f
PLL
, f
OUT
= f
PLL
, f
IN
, x M / [2 x (N+1) x (P+1)]
However, since the following requirements must be satisfied, then not all combinations
of M/N/P are valid:
M must be 16 or higher
f
PFD
, f
VCO
, f
OUT
ranges are satisfied
After determining the proper M, N, and P values and setting them in R102:0/R103:0, the
PLL can be enabled by the following sequence:
R101:0[14] = 0// powers on PLL
R101:0[15] = 0// disable PLL bypass (enabling PLL)
Note: If PLL is used, bypass the PLL (R101:0[15]=1) before going into hard standby. It can be
enabled again (R101:0[15]=0) once the sensor is out of standby.
PLL Power-up
The PLL takes time to power up. During this time, the behavior of its output clock signal
is not guaranteed. The PLL is in the power down mode by default and must be turned on
manually. When using the PLL, the correct power-up sequence after chip reset is as fol-
lows:
1. Program PLL frequency settings (R0x66:0 and R0x67:0)
2. Power up the PLL (R0x65:0[14] = 0)
3. Wait for a time longer than PLL locking time (> 1ms)
4. Turn off the PLL bypass (R0x65:0[15] = 0)
Table 29: Frequency Parameters
Frequency Equation MIN (MHz) MAX (MHz)
f
PFD
f
IN
/ (N+1) 2 13
f
VCO
f
PFD
x M 110 240
f
OUT
f
VCO
/ [2 x (P+1)] 6 80
f
IN
—664