Datasheet

PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__6_REV5.fm - Rev. B 2/06 EN
121 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Sensor Core
Micron Confidential and Proprietary
Registers
Table 5, "Sensor Register Description," on page 29 provides a detailed description of the
registers. Bit fields that are not identified in the table are read only.
Double-Buffered Registers
Some sensor settings cannot be changed during frame readout. For example, changing
row width R0x03:0 part way through frame readout results in inconsistent LINE_VALID
behavior. To avoid this, the sensor core double buffers many registers by implementing a
“pending” and a “live” version. READs and WRITEs access the pending register. The live
register controls the sensor operation.
The value in the pending register is transferred to a live register at a fixed point in the
frame timing, called “frame start.” Frame start is defined as the point at which the first
dark row is read out. By default, this occurs 10 row times before FRAME_VALID goes
HIGH. R0x22:0 enables the dark rows to be shown in the image, but this has no effect on
the position of frame start.
To determine which registers or register fields are double-buffered in this way, see
Table 5, "Sensor Register Description," on page 29, the “sync’d-to-frame-start” column.
R0x0D:0[15] can be used to inhibit transfers from the pending to the live registers. This
control bit should be used when making many register changes that must take effect
simultaneously.
Bad Frames
A bad frame is a frame where all rows do not have the same integration time, or where
offsets to the pixel values changed during the frame.
Many changes to the sensor register settings can cause a bad frame. For example, when
row width R0x03:0 is changed, the new register value does not affect sensor behavior
until the next frame start. However, the frame that would be read out at that frame-start
has been integrated using the old row width. Consequently, reading it out using the new
row width results in a frame with an incorrect integration time.
By default, most bad frames are masked: LINE_VALID and FRAME_VALID are inhibited
for these frames so that the vertical blanking time between frames is extended by the
frame time.
To determine which register or register field changes can produce a bad frame, see
Table 5, "Sensor Register Description," on page 29, the “bad frame” column, and these
notations:
• N—No. Changing the register value does not produce a bad frame
• Y—Yes. Changing the register value might produce a bad frame
• YM—Yes; but the bad frame is masked out unless the “show bad frames” feature
(R0x0D:0[8]) is enabled
Changes to Integration Time
If the integration time (R0x09:0) is changed while FRAME_VALID is asserted for frame n;
the first frame output using the new integration time is frame (n + 2). The sequence is as
follows:
1. During frame n, the new integration time is held in the R0x09:0 pending register.
2. At the start of frame (n +1), the new integration time is transferred to the R0x09:0 live
register.