Datasheet
Table Of Contents
- 1/3.2-Inch System-On-A-Chip (SOC) CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- General Description
- Feature Overview
- Typical Connection
- Ballout and Interface
- Architecture Overview
- Registers and Variables
- Registers
- Registers
- IFP Registers, Page 1
- IFP Registers, Page 2
- JPEG Indirect Registers
- Table 8: JPEG Indirect Registers (See Registers 30 and 31, Page 2)
- Firmware Driver Variables
- Table 9: Drivers IDs
- Table 10: Driver Variables-Monitor Driver (ID = 0)
- Table 11: Driver Variables-Sequencer Driver (ID = 1)
- Table 12: Driver Variables-Auto Exposure Driver (ID = 2)
- Table 13: Driver Variables-Auto White Balance (ID = 3)
- Table 14: Driver Variables-Flicker Detection Driver (ID = 4)
- Table 15: Driver Variables-Auto Focus Driver (ID = 5)
- Table 16: Driver Variables-Auto Focus Mechanics Driver (ID = 6)
- Table 17: Driver Variables-Mode/Context Driver (ID = 7)
- Table 18: Driver Variables-JPEG Driver (ID = 9)
- Table 19: Driver Variables-Histogram Driver (ID = 11)
- MCU Register List and Memory Map
- JPEG Indirect Registers
- Output Format and Timing
- Sensor Core
- Feature Description
- PLL Generated Master Clock
- PLL Setup
- Window Control
- Pixel Border
- Readout Modes
- Figure 20: 6 Pixels in Normal and Column Mirror Readout Modes
- Figure 21: 6 Rows in Normal and Row Mirror Readout Modes
- Table 30: Skip Values
- Figure 22: 8 Pixels in Normal and Column Skip 2x Readout Modes
- Figure 23: 16 Pixels in Normal and Column Skip 4x Readout Modes
- Figure 24: 32 Pixels in Normal and Column Skip 8x Readout Modes
- Figure 25: 64 Pixels in Normal and Column Skip 16x Readout Modes
- Table 31: Row Addressing
- Table 32: Column Addressing
- Frame Rate Control
- Context Switching
- Integration Time
- Flash STROBE
- Global Reset
- Analog Signal Path
- Analog Inputs AIN1-AIN3
- Firmware
- Firmware
- Start-Up and Usage
- General Purpose I/O
- Introduction
- GPIO Output Control Overview
- Waveform Programming
- Notification Signals
- Digital and Analog Inputs
- GPIO Software Drivers
- Auto Focus
- Figure 42: Search for Best Focus
- Figure 43: Scene with Two Potential Focus Targets at Different Distances from Camera
- Figure 44: Dependence of Luminance-Normalized Local Sharpness Scores on Lens Position
- Figure 45: Example of Position Weight Histogram Created by AF Driver
- Figure 46: Auto Focus Windows
- Figure 47: Computation of Sharpness Scores and Luminance Average for an AF Window
- Table 41: Examples of AF Filters that can be Programmed into the MT9D111
- Spectral Characteristics
- Electrical Specifications
- Packaging
- Appendix A: Two-Wire Serial Register Interface
- Protocol
- Sequence
- Bus Idle State
- Start Bit
- Stop Bit
- Slave Address
- Data Bit Transfer
- Acknowledge Bit
- No-Acknowledge Bit
- Page Register
- Sample Write and Read Sequences
- Figure 52: WRITE Timing to R0x09:0-Value 0x0284
- Figure 53: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 54: WRITE Timing to R0x09:0-Value 0x0284
- Figure 55: READ Timing from R0x09:0; Returned Value 0x0284
- Figure 56: Two-Wire Serial Bus Timing Parameters
- Table 46: Two-wire Serial Bus Characteristics
- Revision History
PDF: 09005aef8202ec2e/Source: 09005aef8202ebf7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9D111__6_REV5.fm - Rev. B 2/06 EN
120 ©2004 Micron Technology, Inc. All rights reserved.
MT9D111 - 1/3.2-Inch 2-Megapixel SOC Digital Image Sensor
Sensor Core
Micron Confidential and Proprietary
Note: Skip factor should be multiplied by 2 if binning is enabled.
Table 27: Frame Time
Parameter Name Equation
Default Timing
at 36 MHz Dual ADC Mode
HBLANK_REG Horizontal Blanking
Register
R0x07:0 if R0xF2:0[0] = 0
R0x05:0 if R0xF2:0[0] = 1
0x15C = 348 pixels
VBLANK_REG Vertical Blanking
Register
R0x8:0 if R0xF2:0[1] = 0
R0x6:0 if R0xF2:0[1] = 1
0x20 = 32 rows
ADC_MODE ADC mode
R0xF2:0[3] = 0: R0x20:0[10]
R0xF2:0[3] = 1: R0x21:0[10]
PIXCLK_PERIOD Pixel clock period
ADC_MODE = 0: R0x0A:0[2:0]
ADC_MODE = 1: R0x0A:0[2:0]*2
1 ADC_MODE: 55.556ns
2 ADC_MODE: 27.778ns
S Skip Factor
For skip 2x mode: S = 2
For skip 4x mode: S = 4
For skip 8x mode: S = 8
For skip 16x mode: S = 16
otherwise, S = 1
1
AActive Data Time
(R0x04:0/S) * PIXCLK_PERIOD 1,600 pixel clocks
= 1,600 master
= 44.44µs
P Frame Start/End
Blanking
6 * PIXCLK_PERIOD (can be controlled by
R0x1F:0)
6 pixel clocks
= 12 master
= 0.166µs
Q Horizontal Blanking
HBLANK_REG * PIXCLK_PERIOD 348 pixel clocks
= 348 master
= 9.667µs
A + Q RowTime
((R0x04:0/S) + HBLANK_REG) * PIXCLK_PERIOD 1,948 pixel clocks
= 1,948 master
= 54.112µs
V Vertical Blanking
VBLANK_REG * (A + Q) + (Q - 2*P) 62,672 pixel clocks
= 62,672 master
= 1.741ms
Nrows * (A + Q) Frame Valid Time
(R0x03:0/S) * (A + Q) - (Q - 2*P) 2,337,264 pixel clocks
= 2,337,264 master
= 64.925ms
F Total Frame Time
((R0x03:0/S) + VBLANK_REG) * (A + Q) 2,399,936 pixel clocks
= 2,399,936 master
= 66.665ms
Table 28: Frame—Long Integration Time
Parameter Name Equation (Master Clock)
V’ Vertical Blanking (long integration time)
(R0x09:0 – (R0x03:0)/S) * (A + Q) + (Q - 2*P)
F’ Total Frame Time (long integration time)
(R0x09:0) * (A + Q)